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    Amorphization induced metal-silicon contact formation
    2.
    发明授权
    Amorphization induced metal-silicon contact formation 有权

    公开(公告)号：US10128114B2

    公开(公告)日：2018-11-13

    申请号：US14874623

    申请日：2015-10-05

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Bartlomiej Jan Pawlak

    IPC分类号： H01L21/265

    摘要： A method of forming a metal-silicon contact is provided. Embodiments include forming a metal layer over a substrate; forming an amorphous silicon (a-Si) capping layer over the metal layer; implanting ions to induce an athermal migration of the a-Si capping layer into the metal layer; and annealing the metal layer and the a-Si capping layer to form a metal silicide layer over the substrate.

    TUNNELING FIELD EFFECT TRANSISTOR AND METHODS OF MAKING SUCH A TRANSISTOR
    3.
    发明申请
    TUNNELING FIELD EFFECT TRANSISTOR AND METHODS OF MAKING SUCH A TRANSISTOR 有权
    隧道场效应晶体管及其制作方法

    公开(公告)号：US20160099343A1

    公开(公告)日：2016-04-07

    申请号：US14503587

    申请日：2014-10-01

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Bartlomiej Jan Pawlak

    IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/205 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165

    CPC分类号： H01L29/66977 ,  H01L21/823418 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/66356 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/7827 ,  H01L29/7848

    摘要： One illustrative method of forming a TFET device includes forming a first semiconductor material that extends for a full length of a drain region, a gate region and a source region of the device, masking the drain region while exposing at least a portion of the gate region and exposing the source region, forming a second semiconductor material above the gate region and above the source region, forming a third semiconductor material above the second semiconductor material and above the gate region and above the source region, the third semiconductor material being doped with an opposite type of dopant material than in the first semiconductor material, masking the drain region, and forming a gate structure above at least a portion of the exposed gate region.

    摘要翻译： 形成TFET器件的一个示例性方法包括形成第一半导体材料，其延伸器件的漏极区域，栅极区域和源极区域的整个长度，在暴露栅极区域的至少一部分的同时掩蔽漏极区域 并且在所述源极区域的上方形成第二半导体材料，在所述源极区域的上方形成第二半导体材料，在所述栅极区域的上方，在所述源极区域的上方形成第三半导体材料，在所述第二半导体材料的上方形成第三半导体材料， 相反类型的掺杂剂材料比第一半导体材料中的掩模，掩蔽漏极区域，以及在暴露的栅极区域的至少一部分上方形成栅极结构。

    METHODS OF FORMING A CHANNEL REGION FOR A SEMICONDUCTOR DEVICE BY PERFORMING A TRIPLE CLADDING PROCESS
    4.
    发明申请
    METHODS OF FORMING A CHANNEL REGION FOR A SEMICONDUCTOR DEVICE BY PERFORMING A TRIPLE CLADDING PROCESS 有权
    通过执行三重切割工艺形成半导体器件的通道区域的方法

    公开(公告)号：US20160005834A1

    公开(公告)日：2016-01-07

    申请号：US14322987

    申请日：2014-07-03

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Bartlomiej Jan Pawlak ,  Behtash Behin-Aein ,  Mehdi Salmani-Jelodar

    IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/66795 ,  H01L29/6681

    摘要： One illustrative method disclosed herein includes, among other things, forming a plurality of trenches that define a fin, performing a plurality of epitaxial deposition processes to form first, second and third layers of epi semiconductor material around an exposed portion of the fin, removing the first, second and third layers of epi semiconductor material from above an upper surface of the fin so as to thereby expose the fin, selectively removing the fin relative to the first, second and third layers of epi semiconductor material so as to thereby define two fin structures comprised of the first, second and third layers of epi semiconductor material, and forming a gate structure around a portion of at least one of the fin structures comprised of the first, second and third layers of epi semiconductor material.

    摘要翻译： 本文公开的一种说明性方法包括形成限定翅片的多个沟槽，执行多个外延沉积工艺以在翅片的暴露部分周围形成第一，第二和第三层外延半导体材料，除去 第一层，第二层和第三层外延半导体材料，从翅片的上表面上方，从而露出翅片，相对于第一，第二和第三层外延半导体材料选择性地去除翅片，从而限定两个鳍 由第一层，第二层和第三层外延半导体材料构成的结构，以及围绕由第一，第二和第三层外延半导体材料构成的至少一个鳍结构的一部分形成栅极结构。

    Methods of forming substrates comprised of different semiconductor materials and the resulting device
    8.
    发明授权
    Methods of forming substrates comprised of different semiconductor materials and the resulting device 有权
    形成由不同半导体材料构成的衬底的方法和所得到的器件

    公开(公告)号：US09368578B2

    公开(公告)日：2016-06-14

    申请号：US13758225

    申请日：2013-02-04

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Bartlomiej Jan Pawlak ,  Steven Bentley ,  Ajey Jacob

    IPC分类号： H01L29/66 ,  H01L29/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

    CPC分类号： H01L29/12 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1207 ,  H01L27/1211

    摘要： Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (SRB) layer between the first and second layers, forming a sidewall spacer on the sidewalls of an opening in the second layer, and forming a third semiconductor material in the opening, wherein the first, second and third semiconductor materials are different. A device includes first and second layers of first and second semiconductor materials and an SRB layer positioned above the first layer. The second layer is positioned above a first portion of the SRB layer, a region of a third semiconductor material is in an opening in the second layer and above a second portion of the SRB layer, and an insulating material is positioned between the region comprised of the third semiconductor material and the second layer.

    摘要翻译： 在第一和第二层之间获得由第一半导体材料的第一和第二层和应变释放缓冲层（SRB）层组成的结构，在第二层的开口的侧壁上形成侧壁间隔物，并形成第三半导体 所述开口中的材料，其中所述第一，第二和第三半导体材料是不同的。 一种器件包括第一和第二层第一和第二半导体材料以及位于第一层之上的SRB层。 第二层位于SRB层的第一部分之上，第三半导体材料的区域位于第二层的开口中并且位于SRB层的第二部分之上，并且绝缘材料位于由 第三半导体材料和第二层。

    Fin pitch scaling and active layer isolation
    9.
    发明授权
    Fin pitch scaling and active layer isolation 有权
    鳍间距缩放和有源层隔离

    公开(公告)号：US09076842B2

    公开(公告)日：2015-07-07

    申请号：US14011125

    申请日：2013-08-27

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Steven John Bentley ,  Bartlomiej Jan Pawlak

    IPC分类号： H01L21/302 ,  H01L21/764 ,  H01L29/78 ,  H01L21/02

    CPC分类号： H01L21/764 ,  H01L21/02488 ,  H01L21/02587 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

    摘要： A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.

    摘要翻译： 第一半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个原始硅鳍片。 电介质材料保形地覆盖在第一半导体结构上并凹进以产生电介质层。 第一覆层材料沉积在原始硅鳍片附近，之后去除原始硅片以形成具有与体硅衬底电隔离的两个散热片的第二半导体结构。 第二包层材料被图案化为与第一包层材料相邻以形成具有与体硅衬底电隔离的四个散热片的第三半导体结构。