- 专利标题: Loop optimization for implementing circuit designs in hardware
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申请号: US15730431申请日: 2017-10-11
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公开(公告)号: US10331836B1公开(公告)日: 2019-06-25
- 发明人: Anup Hosangadi , Sumanta Datta , Aman Gayasen , Ashish Sirasao
- 申请人: Xilinx, Inc.
- 申请人地址: US CA San Jose
- 专利权人: XILINX, INC.
- 当前专利权人: XILINX, INC.
- 当前专利权人地址: US CA San Jose
- 代理商 Kevin T. Cuenot
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; H03K19/173
摘要:
Implementing a circuit design can include determining a chain of a plurality of loop elements of a circuit design, wherein each loop element includes a bit select node configured to perform a bit assignment operation and a corresponding address calculation node, wherein the address calculation nodes use a common variable to calculate a starting bit location provided to the corresponding bit select node. In response to the determining, the chain is replicated resulting in one chain for each value of the common variable and transforming each chain into a plurality of wires. A multiplexer is inserted into the circuit design. The plurality of wires for each chain is coupled to inputs of the multiplexer and the common variable is provided to the multiplexer as a select signal.
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