Vertical field-effect transistors are fabricated while controlling gate length by causing enhanced oxidation of silicon germanium regions on parallel semiconductor fin channel regions. Oxidation of the silicon germanium region is accompanied by volume expansion and condensation. Shared or non-shared gate structures are formed on the sidewalls of the semiconductor fin channel regions. A dielectric liner may be incorporated with self-aligned oxide regions to form a composite spacer for providing electrical isolation of the top source/drain regions.