公开(公告)号：US20240405071A1

公开(公告)日：2024-12-05

申请号：US18328871

申请日：2023-06-05

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Julien Frougier ,  Ruilong Xie ,  Min Gyu Sung ,  Chen Zhang

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H10B12/00

Abstract: A semiconductor structure includes a nanosheet field-effect transistor having a nanosheet stack structure, and a fin field-effect transistor having a set of vertical fins. Each of the vertical fins includes an oxide semiconductor material. The nanosheet field-effect transistor and the fin field-effect transistor are in a stacked configuration.

公开(公告)号：US12142526B2

公开(公告)日：2024-11-12

申请号：US17656174

申请日：2022-03-23

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Chen Zhang ,  Heng Wu ,  Julien Frougier ,  Alexander Reznicek

IPC: H01L21/768 ,  H01L29/06 ,  H01L29/417

Abstract: A stacked field-effect transistors (FETs) layout and a method for fabrication are provided. The stacked FETs include a buried interconnect within the stacked devices which provides power to buried components without requiring a wired connection from a top of the stacked FET to the buried components. The buried interconnect allows for efficient scaling of the stacked devices without extraneous wiring from a top of the device to each epitaxial region/device within the overall device.

公开(公告)号：US12108692B2

公开(公告)日：2024-10-01

申请号：US17473359

申请日：2021-09-13

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Tian Shen ,  Kevin W. Brew ,  Jingyun Zhang

IPC: H10N70/20 ,  H10N70/00

CPC classification number: H10N70/253 ,  H10N70/063 ,  H10N70/231 ,  H10N70/823 ,  H10N70/8413 ,  H10N70/8828

Abstract: A phase change memory, a system, and a method to prevent high resistance drift within a phase change memory through a phase change memory cell with three terminals and self-aligned metal contacts. The phase change memory may include a bottom electrode. The phase change memory may also include a heater proximately connected to the bottom electrode. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include metal proximately connected to at least two sides of the phase change material. The phase change memory may also include three terminals, where a bottom terminal is located at an area proximately connected to the heater and two top terminals are located at areas proximately connected to the metal.

公开(公告)号：US12002874B2

公开(公告)日：2024-06-04

申请号：US17384908

申请日：2021-07-26

Applicant: International Business Machines Corporation

Inventor： Junli Wang ,  Ruilong Xie ,  Brent Anderson ,  Chen Zhang ,  Heng Wu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/7851

Abstract: A semiconductor structure includes a power rail contact at least partially disposed between a first source/drain region of a first vertical fin structure and a second source/drain region of a second vertical fin structure. The power rail contact is in contact with a buried power rail disposed under the first and second vertical fin structures. The power rail contact is in contact with at least one of the first and second source/drain regions. A contact cap is disposed above the power rail contact.

公开(公告)号：US20240172454A1

公开(公告)日：2024-05-23

申请号：US18057836

申请日：2022-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Heng Wu ,  Min Gyu Sung ,  Chanro Park

IPC: H10B61/00 ,  H03K19/173 ,  H03K19/20 ,  H10B53/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H01L27/228 ,  H01L27/11502 ,  H01L27/2454 ,  H01L45/04 ,  H03K19/1733 ,  H03K19/20

Abstract: Embodiments of the invention include a transistor coupled to a memory element, the memory element being in series with a first bistable resistive element that is configured to switch between a first low resistance state and a first high resistance state. A logic circuit is coupled to the transistor via a series connection to a second bistable resistive element, the second bistable resistive element being configured to switch between a second low resistance state and a second high resistance state.

公开(公告)号：US11990530B2

公开(公告)日：2024-05-21

申请号：US18317165

申请日：2023-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingyun Zhang ,  Choonghyun Lee ,  Chun Wing Yeung ,  Robin Hsin Kuo Chao ,  Heng Wu

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66522 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02609 ,  H01L21/3065 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/6653 ,  H01L29/78696 ,  H01L29/66545

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

公开(公告)号：US20240128333A1

公开(公告)日：2024-04-18

申请号：US17967428

申请日：2022-10-17

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Chen Zhang ,  Min Gyu Sung ,  Heng Wu

IPC: H01L29/417 ,  H01L21/762 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/76283 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L23/5286

Abstract: A semiconductor structure is provided including a backside source/drain contact structure that contacts a source/drain region of a transistor and overlaps a portion of a tri-layered bottom dielectric isolation structure that is located on a backside of the transistor. The presence of the tri-layered bottom dielectric isolation structure prevents shorting between the gate structure of the transistor and the backside source/drain contact structure, and thus improves process margin.

公开(公告)号：US20240063189A1

公开(公告)日：2024-02-22

申请号：US17820264

申请日：2022-08-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Ruilong Xie ,  Julien Frougier ,  Min Gyu Sung ,  Nicolas Jean Loubet

IPC: H01L25/07 ,  H01L21/822 ,  H01L21/84 ,  H01L27/12 ,  H01L27/06 ,  H01L29/786

CPC classification number: H01L25/074 ,  H01L21/8221 ,  H01L21/845 ,  H01L27/1211 ,  H01L27/0688 ,  H01L29/78696

Abstract: A long channel transistor structure including a first transistor array adjacent to a second transistor array, a third transistor array adjacent to a fourth transistor array, where the third transistor array and the fourth transistor array are arranged above the first transistor array and the second transistor array, and a continuous channel path through channels of the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array.

公开(公告)号：US20230420502A1

公开(公告)日：2023-12-28

申请号：US17808124

申请日：2022-06-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Junli Wang ,  Ruilong Xie ,  Albert M. Young ,  Albert M. Chu ,  Brent A. Anderson ,  Ravikumar Ramachandran

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0673 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66439 ,  H01L21/823412 ,  H01L21/823418

Abstract: A field effect transistor (“FET”) stack, including a lower FET, and an upper FET, a first contact to a lower source drain of the lower FET, a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain, a first overlap region between the first silicide and the first contact is less than a second overlap region between the first silicide and the first source drain. The first contact has a reverse tapper metal stud profile. Forming a first contact to a lower source drain of a lower FET of an FET stack, forming a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain.

公开(公告)号：US20230378259A1

公开(公告)日：2023-11-23

申请号：US17664082

申请日：2022-05-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Heng Wu ,  Julien Frougier ,  Min Gyu Sung

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66545

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet and adjacent source/drain regions are provided, where a dummy gate having a gate cut straddles over the nanosheet stack. A semiconductor layer is wafer bonded. A fin is patterned in the semiconductor layer. A source/drain region is formed. A spacer is formed on the bottom source/drain region. A dummy gate is formed on sidewalls of a portion of the fin. A source/drain region is formed. A trench is formed that passes through one dummy gate to the other dummy gate. The dummy gates are removed. Each sacrificial semiconductor material nanosheet is removed. Functional gate structures are formed in regions occupied by the dummy gates and each sacrificial semiconductor material nanosheet.