- 专利标题: Link training mechanism by controlling delay in data path
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申请号: US15845683申请日: 2017-12-18
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公开(公告)号: US10347347B1公开(公告)日: 2019-07-09
- 发明人: Amit Kumar Srivastava , Sriram Balasubrahmanyam
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Green, Howard & Mughal, LLP
- 主分类号: G11C16/32
- IPC分类号: G11C16/32 ; G11C7/22
摘要:
An apparatus is provided which comprises: a buffer to receive first data from a host, and output the first data with configurable delay; and one or more circuitries to: compare the first data from the host with second data that is accessible to the apparatus, wherein the second data is substantially a copy of the first data, and calibrate the delay of the buffer, based at least in part on the comparison of the first data and the second data.
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