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6 条记录 (耗时 0.016 秒)

    MULTI-PHASE CLOCKING SCHEME FOR A MEMORY DEVICE
    1.
    发明公开
    MULTI-PHASE CLOCKING SCHEME FOR A MEMORY DEVICE 审中-公开

    公开(公告)号：US20230215478A1

    公开(公告)日：2023-07-06

    申请号：US18148230

    申请日：2022-12-29

    申请人： Intel Corporation

    发明人： Sriram Balasubrahmanyam ,  Arti Sharma ,  Jong Tai Park ,  Tri Tran

    IPC分类号： G11C7/22 ,  G11C7/10

    CPC分类号： G11C7/222 ,  G11C7/1066

    摘要： Technology to provide a multi-phase clocking scheme for a memory device includes generating, based on a first clock signal having a first frequency, multi-phase clock signals for a memory device having a second frequency, where the second frequency is a fraction of the first frequency, generating local clock signals for data channels of the memory device based on the multi-phase clock signals, where the local clock signals are synchronous with respective rising edges of the multi-phase clock signals, and providing output data for the data channels of the memory device in an output data sequence based on the local clock signals. In some embodiments, the second frequency is one-half of the first frequency, and the multi-phase clock signals are four-phase clock signals. In some embodiments, the output data is clocked out at an effective rate equal to the first frequency based on the local clock signals.

    Link training mechanism by controlling delay in data path
    2.
    发明授权
    Link training mechanism by controlling delay in data path 有权

    公开(公告)号：US10347347B1

    公开(公告)日：2019-07-09

    申请号：US15845683

    申请日：2017-12-18

    申请人： Intel Corporation

    发明人： Amit Kumar Srivastava ,  Sriram Balasubrahmanyam

    IPC分类号： G11C16/32 ,  G11C7/22

    摘要： An apparatus is provided which comprises: a buffer to receive first data from a host, and output the first data with configurable delay; and one or more circuitries to: compare the first data from the host with second data that is accessible to the apparatus, wherein the second data is substantially a copy of the first data, and calibrate the delay of the buffer, based at least in part on the comparison of the first data and the second data.

    APPARATUS, SYSTEM, AND METHOD FOR N-PHASE DATA MAPPING
    3.
    发明申请
    APPARATUS, SYSTEM, AND METHOD FOR N-PHASE DATA MAPPING 审中-公开
    用于N相数据映射的装置，系统和方法

    公开(公告)号：US20140368667A1

    公开(公告)日：2014-12-18

    申请号：US14142848

    申请日：2013-12-29

    申请人： Intel Corporation

    发明人： Steven A. Peterson ,  Haran Thanigasalam ,  Sriram Balasubrahmanyam

    IPC分类号： H04N17/00

    CPC分类号： H04N17/002 ,  G06F13/4278 ,  H04L7/0066 ,  H04L7/10 ,  H04N5/23203

    摘要： Apparatus, methods, and systems are herein described for providing a method for calibrating a channel by employing a training sequence during at least one blanking interval. In one embodiment, an apparatus includes a first control logic to send a command to generate a predetermined data pattern during at least one blanking interval. In addition, the apparatus includes a second control logic to determine whether a received data pattern matches the predetermined data pattern.

    摘要翻译： 本文描述的装置，方法和系统用于提供一种通过在至少一个消隐间隔期间采用训练序列校准信道的方法。 在一个实施例中，一种装置包括第一控制逻辑，用于在至少一个消隐间隔期间发送命令以产生预定的数据模式。 另外，该装置包括用于确定接收到的数据模式是否与预定数据模式匹配的第二控制逻辑。