公开(公告)号：US12210620B2

公开(公告)日：2025-01-28

申请号：US17203553

申请日：2021-03-16

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: G06F21/55 ,  G06N3/04 ,  G06N3/088

Abstract: Hardware based unsupervised based machine-learning (ML) approach to identify a security threat to the processor (e.g., caused by probing of a power supply rail). An apparatus is provided which includes an on-die power supply droop detector as a feature extractor. The droop detector detects a droop in the power supply caused by a probe physically coupling to the power supply rail. The droop detector in combination with machine-learning logic detects change in power supply rail impedance profile due to a probe coupled to the power supply rail. A deep-neural network (DNN) is provided for feature classification that classifies a security threat from normal operation and from operations caused by aging of devices in the processor. The DNN is trained in a training phase or production phase of the processor. An aging sensor is used to distinguish classification of aged data vs. normal data and data from security attack.

公开(公告)号：US11704274B2

公开(公告)日：2023-07-18

申请号：US17479001

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/4086 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4291

Abstract: In one embodiment, an apparatus includes a host controller to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto a first line of the interconnect; a second driver to drive a clock signal onto a second line of the interconnect; and a mode control circuit to cause the second driver to drive the clock signal onto the second line of the interconnect in a first mode and to cause the first driver and the second driver to drive differential information onto the first line and the second line of the interconnect in a second mode. Other embodiments are described and claimed.

公开(公告)号：US11301406B2

公开(公告)日：2022-04-12

申请号：US15237928

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Duane G. Quiet ,  Kenneth P. Foust

IPC: H04W84/20 ,  G06F13/364 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/42

Abstract: In an embodiment, a host device includes: a transceiver to communicate information on an interconnect; a controller to control operation of the transceiver and to be a master for the interconnect; and a role transfer logic to cause a secondary device to be the master for the interconnect when at least a portion of the host device is to enter into a low power. Other embodiments are described and claimed.

公开(公告)号：US11294846B2

公开(公告)日：2022-04-05

申请号：US15706913

申请日：2017-09-18

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Kenneth P. Foust

IPC: G06F13/42 ,  G06F13/40 ,  G06F21/85 ,  G06F21/62

Abstract: In one embodiment, an apparatus includes: a processing circuit to execute instructions; and a host controller coupled to the processing circuit to perform a key exchange with a second device to couple to the apparatus via a bus to which a plurality of devices may be coupled, and in response to a successful completion of the key exchange, enable secure communication with the second device. Other embodiments are described and claimed.

公开(公告)号：US11226912B2

公开(公告)日：2022-01-18

申请号：US17011877

申请日：2020-09-03

Applicant: Intel Corporation

Inventor： Kenneth P. Foust ,  Duane G. Quiet ,  Amit Kumar Srivastava

IPC: G06F13/24 ,  G06F13/42

Abstract: Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I2C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I2C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I2C OBI, an I3C IBI that includes information related to the I2C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.

公开(公告)号：US11119704B2

公开(公告)日：2021-09-14

申请号：US16367608

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Mikal Hunsaker ,  Karthi R. Vadivelu ,  Rahul Bhatt ,  Kenneth P. Foust ,  Rajesh Bhaskar ,  Amit Kumar Srivastava

IPC: G06F3/06 ,  G06F13/38 ,  G06F9/54

Abstract: In one embodiment, a flash sharing controller is to enable a plurality of components of a platform to share a flash memory. The flash sharing controller may include: a flash sharing class layer including a configuration controller to configure the plurality of components to be flash master devices and configure a flash sharing slave device for the flash memory; and a physical layer coupled to the flash sharing class layer to communicate with the plurality of components via a bus. Other embodiments are described and claimed.

公开(公告)号：US11029750B2

公开(公告)日：2021-06-08

申请号：US15638049

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Chenchu Punnarao Bandi

IPC: G06F1/3287 ,  G06F1/3215 ,  G06F1/3234 ,  G06F13/42 ,  G06F13/40

Abstract: Apparatus for managing high speed Universal Serial Bus 2.0 (USB2) communications is presented. The apparatus may include a combination differential difference detector to receive first and second input signals, the combination differential difference detector to, in a first mode: sense a first voltage difference between the first and second input signals and output a squelch signal when the first voltage difference is less than or equal to a pre-defined value. The combination differential difference detector is to, in a second mode, sense a second voltage difference between the first and second input signals and output a disconnect signal when the second voltage difference is greater than or equal to a pre-defined value. Related methods may also be disclosed.

公开(公告)号：US11016920B2

公开(公告)日：2021-05-25

申请号：US15396179

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Chenchu Punnarao Bandi ,  Amit Kumar Srivastava

IPC: G06F13/40 ,  G06F13/42 ,  G06F15/78 ,  G06F15/76

Abstract: Aspects of the embodiments are directed to calibrating a cross-talk cancellation module. A data eye response for a first data channel can be acquired, and the left-side and right-side maximum transition edges can be determined while adjacent data channels are silent. The adjacent data channels can be activated, first using an even mode waveform. A strobe can be positioned at the left-side maximum boundary in anticipation of a right-shift due to even mode waveform cross talk. A summer circuit can sum the waveform from the first data channel with cross-talk induced voltage pulse having an opposite polarity from the even mode waveforms on the aggressor channels. A left-side edge can be determined by incrementally adjusting gain and detector parameters. These parameters can be locked once a left-side transition edge is located. The process can be repeated for a right-side transition edge with odd-mode aggressor waveforms.

公开(公告)号：US10944408B2

公开(公告)日：2021-03-09

申请号：US16140355

申请日：2018-09-24

Applicant: INTEL CORPORATION

Inventor： Amit Kumar Srivastava

IPC: H04L29/08 ,  H03L1/00 ,  G06F13/42 ,  H04N9/80 ,  H03L7/087 ,  H03L7/23 ,  H03L7/197 ,  H03M1/50

Abstract: Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.

公开(公告)号：US10817454B2

公开(公告)日：2020-10-27

申请号：US16396153

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Chih-Cheh Chen ,  Janusz P. Jurski ,  Amit Kumar Srivastava ,  Malay Trivedi ,  James Mitchell ,  Piotr Michael Kwidzinski ,  David N. Lombard

IPC: G06F13/40 ,  G06F13/42 ,  G06F1/329 ,  G06F1/3234 ,  G06F9/38 ,  G06F1/3228

Abstract: An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.