Invention Grant
- Patent Title: Method and apparatus to enable multiple masters to operate in a single master bus architecture
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Application No.: US15087535Application Date: 2016-03-31
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Publication No.: US10353837B2Publication Date: 2019-07-16
- Inventor: Shoichiro Sengoku , Richard Dominic Wietfeldt , George Alan Wiley
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza LLP
- Main IPC: G06F13/364
- IPC: G06F13/364 ; G06F13/42 ; G06F13/26 ; G06F13/24 ; G06F13/36 ; G06F13/362 ; G06F11/30
Abstract:
To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to assert an in-band IRQ. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.
Public/Granted literature
- US20160217090A1 METHOD AND APPARATUS TO ENABLE MULTIPLE MASTERS TO OPERATE IN A SINGLE MASTER BUS ARCHITECTURE Public/Granted day:2016-07-28
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