Invention Grant
- Patent Title: Copper etching integration scheme
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Application No.: US16017039Application Date: 2018-06-25
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Publication No.: US10354954B2Publication Date: 2019-07-16
- Inventor: Chih-Wei Lu , Chung-Ju Lee , Hsiang-Huan Lee , Tien-I Bao
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/528 ; H01L23/538 ; H01L23/532 ; H01L21/768 ; H01L29/06 ; H01L21/3105 ; H01L21/3213 ; H01L23/522

Abstract:
The present disclosure, in some embodiments, relates to an interconnect structure. The interconnect structure has a metal body disposed over a substrate, and a metal projection protruding outward from an upper surface of the metal body. A dielectric layer is disposed over the substrate and surrounds the metal body and the metal projection. A barrier layer separates the metal body and the metal projection from the dielectric layer.
Public/Granted literature
- US20180301416A1 COPPER ETCHING INTEGRATION SCHEME Public/Granted day:2018-10-18
Information query
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