Invention Grant
- Patent Title: Semiconductor package with multiple stacked leadframes and a method of manufacturing the same
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Application No.: US16243972Application Date: 2019-01-09
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Publication No.: US10361146B2Publication Date: 2019-07-23
- Inventor: Saravuth Sirinorakul , Keith M. Edwards , Suebphong Yenrudee , Albert Loh
- Applicant: UTAC Headquarters PTE. LTD.
- Applicant Address: SG Singapore
- Assignee: UTAC Headquarters PTE, LTD.
- Current Assignee: UTAC Headquarters PTE, LTD.
- Current Assignee Address: SG Singapore
- Agency: Haverstock & Owens LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/495 ; H01L23/31 ; H01L21/78 ; H01L21/48
Abstract:
Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.
Public/Granted literature
- US20190181077A1 SEMICONDUCTOR PACKAGE WITH MULTIPLE STACKED LEADFRAMES AND A METHOD OF MANUFACTURING THE SAME Public/Granted day:2019-06-13
Information query
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