公开(公告)号：US20180061667A1

公开(公告)日：2018-03-01

申请号：US15803605

申请日：2017-11-03

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/48 ,  H01L23/495 ,  H01L21/56

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a leadframe land grid array semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

公开(公告)号：US10163658B2

公开(公告)日：2018-12-25

申请号：US15667433

申请日：2017-08-02

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to activate areas of each molding compound layer of the semiconductor package. Each compound filler in the molding compound layer has a metal interior and an insulating outermost shell. The activated molding compound areas in the molding compound layer become metallized in an electroless plating solution to build conductive paths on the molding compound surface, while properties of non-activated molding compound areas are not changed.

公开(公告)号：US09805955B1

公开(公告)日：2017-10-31

申请号：US15347641

申请日：2016-11-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49527 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49805 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2224/45664 ,  H01L2224/45644

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

公开(公告)号：US20190181077A1

公开(公告)日：2019-06-13

申请号：US16243972

申请日：2019-01-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Keith M. Edwards ,  Suebphong Yenrudee ,  Albert Loh

IPC: H01L23/495 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/49537 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49582 ,  H01L2224/48247 ,  H01L2224/97

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.

公开(公告)号：US10242953B1

公开(公告)日：2019-03-26

申请号：US15167757

申请日：2016-05-27

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Suebphong Yenrudee ,  Chanapat Kongpoung ,  Sant Hongsongkiat ,  Siriwanna Ounkaew ,  Chatchawan Injan ,  Saravuth Sirinorakul

IPC: H01L23/552 ,  H01L23/495 ,  H01L23/31 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: Embodiments of the present invention relate to a semiconductor package with a metal-plated shield. Surfaces of molding compound are roughened by an abrasion process such that the surfaces have an unnatural surface roughness that is rougher than a natural surface roughness. The roughened surfaces provide better adhesion of the metal-plated shield to the roughened surfaces than to untreated surfaces (e.g., surfaces with the natural surface roughness). A catalyst material can be deposited on the roughened surfaces of the molding compound before a metal layer is coated on the roughened surfaces of the molding compound to speed up the time for the metal layer to adhere to the roughened surfaces of the molding compound. The metal-plated shield can include plurality of metal layers plated on top of each other.

公开(公告)号：US10096490B2

公开(公告)日：2018-10-09

申请号：US15674449

申请日：2017-08-10

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/02 ,  H01L21/48 ,  H01L23/498 ,  H01L23/495 ,  H01L23/00

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

公开(公告)号：US09922843B1

公开(公告)日：2018-03-20

申请号：US15347666

申请日：2016-11-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/48 ,  H01L23/495

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49527 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49805 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2224/45664 ,  H01L2224/45644

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to activate areas of each molding compound layer of the semiconductor package. Each compound filler in the molding compound layer has a metal interior and an insulating outermost shell. The activated molding compound areas in the molding compound layer become metallized in an electroless plating solution to build conductive paths on the molding compound surface, while properties of non-activated molding compound areas are not changed.

公开(公告)号：US10276477B1

公开(公告)日：2019-04-30

申请号：US15590878

申请日：2017-05-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Keith M. Edwards ,  Suebphong Yenrudee ,  Albert Loh

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/78

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.

公开(公告)号：US10269686B1

公开(公告)日：2019-04-23

申请号：US15167724

申请日：2016-05-27

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Suebphong Yenrudee ,  Saravuth Sirinorakul

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/311 ,  H01L21/48 ,  H01L21/683

Abstract: Embodiments of the present invention relate to a semiconductor package that includes a locking feature. The locking feature is provided by an unnatural surface roughness of a first molding compound to increase adhesion with a second molding compound. Surfaces of first molding compound are roughened by an abrasion process such that the surfaces are rougher than a natural surface roughness. The roughened surfaces of the first molding compound provide better adhesion of the second molding compound to the roughened surfaces than to untreated surfaces (e.g., surfaces with the natural surface roughness).

公开(公告)号：US09917038B1

公开(公告)日：2018-03-13

申请号：US15347599

申请日：2016-11-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49527 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49805 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2224/45664 ,  H01L2224/45644

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.