公开(公告)号：US20220077019A1

公开(公告)日：2022-03-10

申请号：US17444611

申请日：2021-08-06

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Saravuth Sirinorakul ,  Preecha Joymak ,  Natawat Kasikornrungroj ,  Wasu Aingkaew ,  Kawin Saiubol ,  Thanawat Jaengkrajarng

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor device has a semiconductor die with a sensor and a cavity formed into a first surface of the semiconductor die to provide access to the sensor. A protective layer is formed on the first surface of the semiconductor die around the cavity. An encapsulant is deposited around the semiconductor die. The protective layer blocks the encapsulant from entering the cavity. With the cavity clear of encapsulant, liquid or gas has unobstructed entry into cavity during operation of the semiconductor die. The clear entry for the cavity provides reliable sensor detection and measurement. The semiconductor die is disposed over a leadframe. The semiconductor die has a sensor. The protective layer can be a film. The protective layer can have a beveled surface. A surface of the leadframe can be exposed from the encapsulant. A second surface of the semiconductor die can be exposed from the encapsulant.

公开(公告)号：US20180061667A1

公开(公告)日：2018-03-01

申请号：US15803605

申请日：2017-11-03

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/48 ,  H01L23/495 ,  H01L21/56

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a leadframe land grid array semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

公开(公告)号：US09741642B1

公开(公告)日：2017-08-22

申请号：US15042050

申请日：2016-02-11

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Somchai Nondhasitthichai ,  Saravuth Sirinorakul ,  Woraya Benjasukul

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/4821 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact side surfaces. The semiconductor package includes a top surface, a bottom surface opposite the top surface, and side surfaces between the top and bottom surfaces. Contacts are located on peripheral edges of the bottom surface. Each of the contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a third surface between the first surface and the second surface. Each of the side surfaces can include a step such that the area of the bottom surface is differently sized from the area of the top surface and the third surface is located at the step. The first surface is plated, while the second surface is exposed (not plated). At least a portion of the third surface is plated.

公开(公告)号：US09564387B2

公开(公告)日：2017-02-07

申请号：US14794715

申请日：2015-07-08

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Saravuth Sirinorakul ,  Antonio Bambalan Dimaano, Jr. ,  Rui Huang

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49541 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4832 ,  H01L21/565 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48249 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399

Abstract: A method of and device for making a semiconductor package. The method comprises etching a first side of a metallic piece forming a leadframe with one or more wire bonding pads, applying a first protective layer on the first side, etching a second side of the metallic piece forming one or more conductive terminals, and applying a second protective layer on the second side. The semiconductor package comprises wire bonding pads in pillars structure surrounding a die attached to the leadframe. One or more terminals are on the bottom side of the semiconductor package.

Abstract translation: 一种用于制造半导体封装的方法和装置。 该方法包括使用一个或多个引线接合焊盘蚀刻形成引线框架的金属片的第一侧，在第一侧上施加第一保护层，蚀刻形成一个或多个导电端子的金属片的第二侧， 第二侧的第二保护层。 半导体封装包括围绕附接到引线框架的管芯的柱状结构的引线接合焊盘。 一个或多个端子位于半导体封装的底侧。

公开(公告)号：US11804416B2

公开(公告)日：2023-10-31

申请号：US17444611

申请日：2021-08-06

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Saravuth Sirinorakul ,  Preecha Joymak ,  Natawat Kasikornrungroj ,  Wasu Aingkaew ,  Kawin Saiubol ,  Thanawat Jaengkrajarng

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3185 ,  H01L21/565 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32155 ,  H01L2924/10157

Abstract: A semiconductor device has a semiconductor die with a sensor and a cavity formed into a first surface of the semiconductor die to provide access to the sensor. A protective layer is formed on the first surface of the semiconductor die around the cavity. An encapsulant is deposited around the semiconductor die. The protective layer blocks the encapsulant from entering the cavity. With the cavity clear of encapsulant, liquid or gas has unobstructed entry into cavity during operation of the semiconductor die. The clear entry for the cavity provides reliable sensor detection and measurement. The semiconductor die is disposed over a leadframe. The semiconductor die has a sensor. The protective layer can be a film. The protective layer can have a beveled surface. A surface of the leadframe can be exposed from the encapsulant. A second surface of the semiconductor die can be exposed from the encapsulant.

公开(公告)号：US11139233B2

公开(公告)日：2021-10-05

申请号：US16886728

申请日：2020-05-28

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Hua Hong Tan ,  Wilson Poh Leng Ong ,  Kriangsak Sae Le ,  Saravuth Sirinorakul ,  Somsak Phukronghin ,  Paweena Phatto

IPC: H01L23/498 ,  H01L23/16 ,  H01L21/48 ,  H01L23/31 ,  H01L21/52 ,  H01L21/56 ,  H01L23/055 ,  H01L23/04 ,  H01L23/24 ,  H01L23/00

Abstract: A method for forming a semiconductor package is disclosed herein. The method includes forming a package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate includes a recess region below the first major surface defined with a die region and a non-die region surrounding the die region. A semiconductor die is disposed in the die region within the recess region. A dam structure is disposed within the recess region. The dam structure surrounds the semiconductor die and extends upwardly to a height below the first major surface of the package substrate. The method also includes dispensing a liquid encapsulant material into the recess region. The liquid encapsulant material is surrounded by the dam structure and extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.

公开(公告)号：US20190181077A1

公开(公告)日：2019-06-13

申请号：US16243972

申请日：2019-01-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Keith M. Edwards ,  Suebphong Yenrudee ,  Albert Loh

IPC: H01L23/495 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/49537 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49582 ,  H01L2224/48247 ,  H01L2224/97

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.

公开(公告)号：US10242953B1

公开(公告)日：2019-03-26

申请号：US15167757

申请日：2016-05-27

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Suebphong Yenrudee ,  Chanapat Kongpoung ,  Sant Hongsongkiat ,  Siriwanna Ounkaew ,  Chatchawan Injan ,  Saravuth Sirinorakul

IPC: H01L23/552 ,  H01L23/495 ,  H01L23/31 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: Embodiments of the present invention relate to a semiconductor package with a metal-plated shield. Surfaces of molding compound are roughened by an abrasion process such that the surfaces have an unnatural surface roughness that is rougher than a natural surface roughness. The roughened surfaces provide better adhesion of the metal-plated shield to the roughened surfaces than to untreated surfaces (e.g., surfaces with the natural surface roughness). A catalyst material can be deposited on the roughened surfaces of the molding compound before a metal layer is coated on the roughened surfaces of the molding compound to speed up the time for the metal layer to adhere to the roughened surfaces of the molding compound. The metal-plated shield can include plurality of metal layers plated on top of each other.

公开(公告)号：US10096490B2

公开(公告)日：2018-10-09

申请号：US15674449

申请日：2017-08-10

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/02 ,  H01L21/48 ,  H01L23/498 ,  H01L23/495 ,  H01L23/00

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

公开(公告)号：US09922843B1

公开(公告)日：2018-03-20

申请号：US15347666

申请日：2016-11-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/48 ,  H01L23/495

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49527 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49805 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2224/45664 ,  H01L2224/45644

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to activate areas of each molding compound layer of the semiconductor package. Each compound filler in the molding compound layer has a metal interior and an insulating outermost shell. The activated molding compound areas in the molding compound layer become metallized in an electroless plating solution to build conductive paths on the molding compound surface, while properties of non-activated molding compound areas are not changed.