公开(公告)号：US10361146B2

公开(公告)日：2019-07-23

申请号：US16243972

申请日：2019-01-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Keith M. Edwards ,  Suebphong Yenrudee ,  Albert Loh

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/78 ,  H01L21/48

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.

公开(公告)号：US20190181077A1

公开(公告)日：2019-06-13

申请号：US16243972

申请日：2019-01-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Keith M. Edwards ,  Suebphong Yenrudee ,  Albert Loh

IPC: H01L23/495 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/49537 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49582 ,  H01L2224/48247 ,  H01L2224/97

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.

公开(公告)号：US10276477B1

公开(公告)日：2019-04-30

申请号：US15590878

申请日：2017-05-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Keith M. Edwards ,  Suebphong Yenrudee ,  Albert Loh

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/78

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.