Invention Grant
- Patent Title: Method for fabricating a JFET transistor within an integrated circuit and corresponding integrated circuit
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Application No.: US15133595Application Date: 2016-04-20
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Publication No.: US10361188B2Publication Date: 2019-07-23
- Inventor: Jean Jimenez
- Applicant: STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Crowe & Dunlevy
- Priority: FR1562956 20151221
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L29/66 ; H01L27/082 ; H01L27/092 ; H01L29/732 ; H01L29/808 ; H01L21/8228 ; H01L21/8238 ; H01L21/8249
Abstract:
An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.
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