公开(公告)号：US20170179113A1

公开(公告)日：2017-06-22

申请号：US15133595

申请日：2016-04-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez

IPC: H01L27/06 ,  H01L27/082 ,  H01L29/66 ,  H01L21/8249 ,  H01L21/8238 ,  H01L21/8228 ,  H01L27/092 ,  H01L29/808

CPC classification number: H01L27/0623 ,  H01L21/82285 ,  H01L21/823885 ,  H01L21/8249 ,  H01L27/0826 ,  H01L27/092 ,  H01L29/66909 ,  H01L29/732 ,  H01L29/8083

Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.

公开(公告)号：US09368611B2

公开(公告)日：2016-06-14

申请号：US13853111

申请日：2013-03-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS S.A.

Inventor： Philippe Galy ,  Patrice Dehan ,  Boris Heitz ,  Jean Jimenez

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L27/07

CPC classification number: H01L29/78 ,  H01L27/0727 ,  H01L29/41775 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66643 ,  H01L29/7839

Abstract: An integrated circuit may include at least one MOS transistor having a sigmoid response. The at least one MOS transistor may include a substrate, a source region, a drain region, a gate region, and insulating spacer regions on either side of the gate region. The substrate may include a first region situated under the gate region between the insulating spacer regions. At least one of the source and drain regions may be separated from the first region of the substrate by a second region of the substrate situated under an insulating spacer region, which may be of a same type of conductivity as the first region of the substrate.

Abstract translation: 集成电路可以包括具有S形响应的至少一个MOS晶体管。 至少一个MOS晶体管可以包括栅极区域的任一侧上的衬底，源极区域，漏极区域，栅极区域和绝缘间隔区域。 衬底可以包括位于绝缘间隔区之间的栅极区域下方的第一区域。 源极和漏极区域中的至少一个可以通过位于绝缘间隔区域下方的衬底的第二区域与衬底的第一区域分离，绝缘间隔区域可以具有与衬底的第一区域相同类型的导电性。

公开(公告)号：US20170194350A1

公开(公告)日：2017-07-06

申请号：US15137540

申请日：2016-04-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez

IPC: H01L27/12 ,  H01L29/10 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78696

Abstract: An integrated circuit includes a MOS transistor situated in and on an active region of a semiconductor substrate. The active region is bounded by an insulating region for example of the shallow trench isolation type. The drain region of the transistor is positioned in the semiconductor substrate situated away from the insulating region. An insulated gate of the transistor includes a central opening that is positioned in alignment with the drain region. A channel region of the transistor is annularly surrounds the drain region.

公开(公告)号：US10361188B2

公开(公告)日：2019-07-23

申请号：US15133595

申请日：2016-04-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez

IPC: H01L27/06 ,  H01L29/66 ,  H01L27/082 ,  H01L27/092 ,  H01L29/732 ,  H01L29/808 ,  H01L21/8228 ,  H01L21/8238 ,  H01L21/8249

Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.

公开(公告)号：US20140124866A1

公开(公告)日：2014-05-08

申请号：US13853111

申请日：2013-03-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS S.A.

Inventor： Philippe Galy ,  Patrice Dehan ,  Boris Heitz ,  Jean Jimenez

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L27/0727 ,  H01L29/41775 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66643 ,  H01L29/7839

Abstract: An integrated circuit may include at least one MOS transistor having a sigmoid response. The at least one MOS transistor may include a substrate, a source region, a drain region, a gate region, and insulating spacer regions on either side of the gate region. The substrate may include a first region situated under the gate region between the insulating spacer regions. At least one of the source and drain regions may be separated from the first region of the substrate by a second region of the substrate situated under an insulating spacer region, which may be of a same type of conductivity as the first region of the substrate.

Abstract translation: 集成电路可以包括具有S形响应的至少一个MOS晶体管。 至少一个MOS晶体管可以包括栅极区域的任一侧上的衬底，源极区域，漏极区域，栅极区域和绝缘间隔区域。 衬底可以包括位于绝缘间隔区之间的栅极区域下方的第一区域。 源极和漏极区域中的至少一个可以通过位于绝缘间隔区域下方的衬底的第二区域与衬底的第一区域分离，绝缘间隔区域可以具有与衬底的第一区域相同类型的导电性。