Invention Grant
- Patent Title: High performance interconnect link layer
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Application No.: US15706191Application Date: 2017-09-15
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Publication No.: US10365965B2Publication Date: 2019-07-30
- Inventor: Jeff Willey , Robert G. Blankenship , Jeffrey C. Swanson , Robert J. Safranek
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F13/42 ; H03M13/09 ; H03M13/00 ; H04L12/46

Abstract:
Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
Public/Granted literature
- US20180011759A1 HIGH PERFORMANCE INTERCONNECT LINK LAYER Public/Granted day:2018-01-11
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