公开(公告)号：US11003610B2

公开(公告)日：2021-05-11

申请号：US16779377

申请日：2020-01-31

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobel Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/12 ,  G06F15/173 ,  G06F1/10

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US20210117350A1

公开(公告)日：2021-04-22

申请号：US17134242

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  H04L12/933 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  G06F9/46 ,  G06F13/40 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US20180300275A1

公开(公告)日：2018-10-18

申请号：US15821492

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Zuoguo J. Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC: G06F13/40 ,  G06F1/10

CPC classification number: G06F13/4022 ,  G06F1/10 ,  G06F13/124 ,  G06F13/4273 ,  G06F13/4282 ,  G06F15/173 ,  Y02D10/14 ,  Y02D10/151

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US09785556B2

公开(公告)日：2017-10-10

申请号：US14582148

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Ramacharan Sundararaman ,  Tracey L. Gustafson ,  Robert J. Safranek

IPC: G06F12/08 ,  G06F12/0831

CPC classification number: G06F12/0831 ,  G06F12/0833 ,  G06F2212/621 ,  Y02D10/13

Abstract: Methods and apparatus relating to techniques for Cross-Die Interface (CDI) snoop and/or go (or completion) message ordering are described. In one embodiment, the order of a snoop message and a completion message are determined based at least on status of two bits. The snoop and completion messages are exchanged between a first integrated circuit die and a second integrated circuit die. The first integrated circuit die and the second integrated circuit die are coupled through a first interface and a second interface and the snoop message and the completion message are exchanged over at least one of the first interface and the second interface. Other embodiments are also disclosed.

公开(公告)号：US12189550B2

公开(公告)日：2025-01-07

申请号：US18347236

申请日：2023-07-05

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F9/445 ,  G06F9/46 ,  G06F11/10 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/40 ,  G06F13/42 ,  H04L9/06 ,  H04L49/15 ,  G06F8/73 ,  H04L12/46 ,  H04L45/74

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US11061850B2

公开(公告)日：2021-07-13

申请号：US16708042

申请日：2019-12-09

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Debendra Das Sharma

IPC: G06F13/42 ,  G06F13/14 ,  G06F13/38 ,  H04L12/00 ,  G06F13/00 ,  G06F12/0831 ,  G06F15/78

Abstract: Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers.

公开(公告)号：US20200320031A1

公开(公告)日：2020-10-08

申请号：US16779377

申请日：2020-01-31

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/12 ,  G06F15/173 ,  G06F1/10

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US10552357B2

公开(公告)日：2020-02-04

申请号：US15821492

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Zuoguo J. Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/12 ,  G06F15/173 ,  G06F1/10

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US10248591B2

公开(公告)日：2019-04-02

申请号：US15393153

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert H. Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  H04L12/933 ,  G06F9/46 ,  G06F13/40 ,  G06F12/0813 ,  G06F12/0815 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808 ,  H04L12/741 ,  G06F8/73 ,  H04L12/46

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US20180011759A1

公开(公告)日：2018-01-11

申请号：US15706191

申请日：2017-09-15

Applicant: Intel Corporation

Inventor： Jeff Willey ,  Robert G. Blankenship ,  Jeffrey C. Swanson ,  Robert J. Safranek

IPC: G06F11/10 ,  G06F13/42 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026 ,  H03M13/09 ,  H04L12/4641

Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.