Invention Grant
- Patent Title: Bit error protection in cache memories
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Application No.: US15489438Application Date: 2017-04-17
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Publication No.: US10379944B2Publication Date: 2019-08-13
- Inventor: John Kalamatianos , Shrikanth Ganapathy , Steven Raasch
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Park, Vaughan, Fleming & Dowler LLP
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/10 ; G11C29/42 ; H03M13/19

Abstract:
A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.
Public/Granted literature
- US20180302105A1 Bit Error Protection in Cache Memories Public/Granted day:2018-10-18
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