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公开(公告)号：US20230153218A1
公开(公告)日：2023-05-18
申请号：US17526218
申请日：2021-11-15
Applicant: Advanced Micro Devices, Inc.
Inventor： Shrikanth Ganapathy , Yasuko Eckert , Anthony Gutierrez , Karthik Ramu Sangaiah , Vedula Venkata Srikant Bharadwaj
CPC classification number: G06F11/3051 , G06F15/80 , G06F11/3024
Abstract: A processor includes a controller and plurality of chiplets, each chiplet including a plurality of processor cores. The controller provides chiplet-level performance information for the chiplets that identifies a performance of each chiplet at each of a plurality of performance levels for specified sets of processor cores on that chiplet. The controller receives an identification of one or more selected chiplets from among the plurality of chiplets for which a specified number of processor cores are to be configured at a given performance level, the one or more selected chiplets having been selected based on the chiplet-level performance information and performance requirements. The controller configures the specified number of processor cores of the one or more selected chiplets at the given performance level. A task is then run on the specified number of processor cores of the one or more selected chiplets at the given performance level.
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公开(公告)号：US11874739B2
公开(公告)日：2024-01-16
申请号：US17033398
申请日：2020-09-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Sudhanva Gurumurthi , Vilas Sridharan , Shaizeen Aga , Nuwan Jayasena , Michael Ignatowski , Shrikanth Ganapathy , John Kalamatianos
CPC classification number: G06F11/1076 , G06F21/602 , H04L9/32
Abstract: A memory module includes one or more programmable ECC engines that may be programed by a host processing element with a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode corrupted data that cannot be corrected, etc. The approach allows an SoC designer or company to program and reprogram ECC engines in memory modules in a secure manner without having to disclose the particular ECC implementations used by the ECC engines to memory vendors or third parties.
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公开(公告)号：US11509333B2
公开(公告)日：2022-11-22
申请号：US17125145
申请日：2020-12-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Shrikanth Ganapathy , John Kalamatianos
IPC: G11C29/00 , H03M13/35 , G06F12/0895 , G06F11/10
Abstract: Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.
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公开(公告)号：US10379944B2
公开(公告)日：2019-08-13
申请号：US15489438
申请日：2017-04-17
Applicant: Advanced Micro Devices, Inc.
Inventor： John Kalamatianos , Shrikanth Ganapathy , Steven Raasch
Abstract: A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.
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公开(公告)号：US20220206899A1
公开(公告)日：2022-06-30
申请号：US17133843
申请日：2020-12-24
Applicant: Advanced Micro Devices, Inc.
Inventor： John Kalamatianos , Nuwan Jayasena , Sudhanva Gurumurthi , Shaizeen Aga , Shrikanth Ganapathy
Abstract: Methods and processing devices are provided for error protection to support instruction replay for executing idempotent instructions at a processing in memory PIM device. The processing apparatus includes a PIM device configured to execute an idempotent instruction. The processing apparatus also includes a processor, in communication with the PIM device, configured to issue the idempotent instruction to the PIM device for execution at the PIM device and reissue the idempotent instruction to the PIM device when one of execution of the idempotent instruction at the PIM device results in an error and a predetermined latency period expires from when the idempotent instruction is issued.
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Patent Agency Ranking
公开(公告)号：US20200081771A1
公开(公告)日：2020-03-12
申请号：US16123489
申请日：2018-09-06
Applicant: Advanced Micro Devices, Inc.
Inventor： John Kalamatianos , Shrikanth Ganapathy
IPC: G06F11/10 , G06F12/0804 , G06F12/0815
Abstract: A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an error protection from among a plurality of error protections. The cache controller uses the selected error protection to protect the data stored in the portion of the cache memory from errors.
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公开(公告)号：US20200073845A1
公开(公告)日：2020-03-05
申请号：US16118172
申请日：2018-08-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Shomit N. Das , Matthew Tomei , Shrikanth Ganapathy , John Kalamatianos
Abstract: Systems, apparatuses, and methods for reliably transmitting data over voltage scaled links are disclosed. A computing system includes at least first and second devices connected via a link. In one implementation, if a data block can be compressed to less than or equal to half the original size of the data block, then the data block is compressed and sent on the link in a single clock cycle rather than two clock cycles. If the data block cannot be compressed to half the original size, but if the data block can be compressed enough to include error correction code (ECC) bits without exceeding the original size, then ECC bits are added to the compressed block which is sent on the link at a reduced voltage. The ECC bits help to correct for any errors that are generated as a result of operating the link at the reduced voltage.
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公开(公告)号：US11797410B2
公开(公告)日：2023-10-24
申请号：US17526218
申请日：2021-11-15
Applicant: Advanced Micro Devices, Inc.
Inventor： Shrikanth Ganapathy , Yasuko Eckert , Anthony Gutierrez , Karthik Ramu Sangaiah , Vedula Venkata Srikant Bharadwaj
CPC classification number: G06F11/3051 , G06F11/3024 , G06F15/80 , G06F11/3409 , Y02D10/00
Abstract: A processor includes a controller and plurality of chiplets, each chiplet including a plurality of processor cores. The controller provides chiplet-level performance information for the chiplets that identifies a performance of each chiplet at each of a plurality of performance levels for specified sets of processor cores on that chiplet. The controller receives an identification of one or more selected chiplets from among the plurality of chiplets for which a specified number of processor cores are to be configured at a given performance level, the one or more selected chiplets having been selected based on the chiplet-level performance information and performance requirements. The controller configures the specified number of processor cores of the one or more selected chiplets at the given performance level. A task is then run on the specified number of processor cores of the one or more selected chiplets at the given performance level.
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公开(公告)号：US10908991B2
公开(公告)日：2021-02-02
申请号：US16123489
申请日：2018-09-06
Applicant: Advanced Micro Devices, Inc.
Inventor： John Kalamatianos , Shrikanth Ganapathy
IPC: G06F11/10 , G06F12/0815 , G06F12/0804
Abstract: A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an error protection from among a plurality of error protections. The cache controller uses the selected error protection to protect the data stored in the portion of the cache memory from errors.
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公开(公告)号：US10558606B1
公开(公告)日：2020-02-11
申请号：US16118172
申请日：2018-08-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Shomit N. Das , Matthew Tomei , Shrikanth Ganapathy , John Kalamatianos
IPC: G06F13/42 , G06F1/3296 , H03M13/05
Abstract: Systems, apparatuses, and methods for reliably transmitting data over voltage scaled links are disclosed. A computing system includes at least first and second devices connected via a link. In one implementation, if a data block can be compressed to less than or equal to half the original size of the data block, then the data block is compressed and sent on the link in a single clock cycle rather than two clock cycles. If the data block cannot be compressed to half the original size, but if the data block can be compressed enough to include error correction code (ECC) bits without exceeding the original size, then ECC bits are added to the compressed block which is sent on the link at a reduced voltage. The ECC bits help to correct for any errors that are generated as a result of operating the link at the reduced voltage.
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