Invention Grant
- Patent Title: Wafer edge partial die engineered for stacked die yield
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Application No.: US15907034Application Date: 2018-02-27
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Publication No.: US10431565B1Publication Date: 2019-10-01
- Inventor: Myongseob Kim , Henley Liu , Cheang-Whang Chang
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/522 ; H01L25/00 ; H01L23/00

Abstract:
A stacked wafer assembly and method for fabricating the same are described herein. In one example, a stacked wafer assembly includes a first wafer bonded to a second wafer. The first wafer includes a plurality of fully functional dies and a first partial die formed thereon. The second wafer includes a plurality of fully functional dies and a first partial die formed thereon. Bond pads formed over an inductor of the first partial die of the first wafer are bonded to bond pads formed on the first partial die of the second wafer to establish electrical connection therebetween.
Information query
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