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    Integrated circuit (IC) structure protection scheme
    1.
    发明授权
    Integrated circuit (IC) structure protection scheme 有权

    公开(公告)号：US12068257B1

    公开(公告)日：2024-08-20

    申请号：US17136721

    申请日：2020-12-29

    Applicant: XILINX, INC.

    Inventor： Myongseob Kim ,  Henley Liu ,  Yun Wu ,  Cheang Whang Chang

    IPC: H01L23/552 ,  H01L21/50 ,  H01L23/528

    CPC classification number: H01L23/552 ,  H01L21/50 ,  H01L23/528

    Abstract: Some examples described herein relate to protecting an integrated circuit (IC) structure from imaging or access. In an example, an IC structure includes a semiconductor substrate, an electromagnetic radiation blocking layer, and a support substrate. The semiconductor substrate has a circuit disposed on a front side of the semiconductor substrate. The electromagnetic radiation blocking layer is disposed on a backside of the semiconductor substrate opposite from the front side of the semiconductor substrate. The support substrate is bonded to the semiconductor substrate. The electromagnetic radiation blocking layer is disposed between the semiconductor substrate and the support substrate.

    Multi-die device structures and methods
    4.
    发明授权
    Multi-die device structures and methods 有权

    公开(公告)号：US11114360B1

    公开(公告)日：2021-09-07

    申请号：US16580620

    申请日：2019-09-24

    Applicant: XILINX, INC.

    Inventor： Jaspreet Singh Gandhi ,  Myongseob Kim

    IPC: H01L25/065 ,  H01L23/31 ,  H01L21/3065 ,  H01L23/498 ,  H01L21/56

    Abstract: Examples described herein provide techniques for multi-die device structures having improved gap uniformity between neighboring dies. In some examples, a first die and a second die are attached to an interposer. A first gap is defined by and between the first die and the second die. At least one of the first die or the second die is etched at the first gap. The etching defines a second gap defined by and between the first die and the second die. The first die, the second die, and the interposer are encapsulated with an encapsulant. The encapsulant is disposed in the second gap.

    METHOD OF TESTING A SEMICONDUCTOR STRUCTURE
    5.
    发明申请
    METHOD OF TESTING A SEMICONDUCTOR STRUCTURE 有权
    测试半导体结构的方法

    公开(公告)号：US20140091819A1

    公开(公告)日：2014-04-03

    申请号：US13630215

    申请日：2012-09-28

    Applicant: XILINX, INC.

    Inventor： Yuqing Gong ,  Henley Liu ,  Myongseob Kim ,  Suresh P. Parameswaran ,  Cheang-Whang Chang ,  Boon Y. Ang

    IPC: G01R31/3187

    CPC classification number: G01R31/31926 ,  G01R31/2812 ,  G01R31/31717 ,  G01R31/31723 ,  H01L2224/16225 ,  H01L2924/15311

    Abstract: An integrated circuit (IC) comprises routing circuitry including a plurality of signal line segments in routing layers of the IC, and a plurality of micro-bump contacts coupled to the routing circuitry. The IC includes a plurality of test circuits coupled to respective subsets of the plurality of signal line segments. Each test circuit is configured to connect micro-bump contacts in the respective subset to form first and second sets of daisy chains. Each test circuit is configured to test the first and second sets of daisy chains for open circuits and test for short circuits between the first and second sets of daisy chains. Each test circuit is configured to determine the locations of detected open circuits and determine the locations of detected short circuits.

    Abstract translation: 集成电路（IC）包括路由电路，其包括在IC的路由层中的多个信号线段以及耦合到路由电路的多个微突点接触。 IC包括耦合到多个信号线段的相应子集的多个测试电路。 每个测试电路被配置为连接相应子集中的微凸块触点以形成第一组和第二组菊花链。 每个测试电路被配置为测试用于开路的第一和第二组菊花链，并测试第一组和第二组菊花链之间的短路。 每个测试电路被配置为确定检测到的开路的位置并确定检测到的短路的位置。

    Method of testing a semiconductor structure
    8.
    发明授权
    Method of testing a semiconductor structure 有权
    测试半导体结构的方法

    公开(公告)号：US08810269B2

    公开(公告)日：2014-08-19

    申请号：US13630215

    申请日：2012-09-28

    Applicant: Xilinx, Inc.

    Inventor： Yuqing Gong ,  Henley Liu ,  Myongseob Kim ,  Suresh P. Parameswaran ,  Cheang-Whang Chang ,  Boon Y. Ang

    IPC: G01R31/3187

    CPC classification number: G01R31/31926 ,  G01R31/2812 ,  G01R31/31717 ,  G01R31/31723 ,  H01L2224/16225 ,  H01L2924/15311

    Abstract: An integrated circuit (IC) comprises routing circuitry including a plurality of signal line segments in routing layers of the IC, and a plurality of micro-bump contacts coupled to the routing circuitry. The IC includes a plurality of test circuits coupled to respective subsets of the plurality of signal line segments. Each test circuit is configured to connect micro-bump contacts in the respective subset to form first and second sets of daisy chains. Each test circuit is configured to test the first and second sets of daisy chains for open circuits and test for short circuits between the first and second sets of daisy chains. Each test circuit is configured to determine the locations of detected open circuits and determine the locations of detected short circuits.

    Abstract translation: 集成电路（IC）包括路由电路，其包括在IC的路由层中的多个信号线段以及耦合到路由电路的多个微突点接触。 IC包括耦合到多个信号线段的相应子集的多个测试电路。 每个测试电路被配置为连接相应子集中的微凸块触点以形成第一组和第二组菊花链。 每个测试电路被配置为测试用于开路的第一和第二组菊花链，并测试第一组和第二组菊花链之间的短路。 每个测试电路被配置为确定检测到的开路的位置并确定检测到的短路的位置。

    IC die with dummy structures
    9.
    发明授权
    IC die with dummy structures 有权

    公开(公告)号：US11114344B1

    公开(公告)日：2021-09-07

    申请号：US16805398

    申请日：2020-02-28

    Applicant: XILINX, INC.

    Inventor： Hui-Wen Lin ,  Nui Chong ,  Myongseob Kim ,  Henley Liu ,  Ping-Chin Yeh ,  Cheang-whang Chang

    IPC: H01L21/82 ,  H01L23/50 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105

    Abstract: Integrated circuit (IC) dies and method for manufacturing the same are described herein that mitigate pattern loading effects during manufacture. In one example, the IC includes a die body having a first circuit block separated from an adjacent second circuit block by a buffer zone. The first and second circuit blocks have first and second transistors that are at least partially fabricated from a gate metal layer and disposed immediately adjacent the buffer zone. A dummy structure is formed in the buffer zone and is also at least partially fabricated from the gate metal layer. An amount of gate metal layer material in the dummy structure is selected to mitigate differences in the amount of gate metal layer material in regions of first and second circuit blocks that neighbor each other across the buffer zone.

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