Invention Grant
- Patent Title: Making electrical components in handle wafers of integrated circuit packages
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Application No.: US16272736Application Date: 2019-02-11
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Publication No.: US10431648B2Publication Date: 2019-10-01
- Inventor: Liang Wang , Hong Shen , Rajesh Katkar
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L49/02 ; H01L23/00 ; H01L25/10 ; H01L25/11 ; H01L25/16 ; H01L25/00 ; H01L23/522 ; H01L23/498

Abstract:
Each of a first and a second integrated circuit structures has hole(s) in the top surface, and capacitors at least partially located in the holes. A semiconductor die is attached to the top surface of the second structure. Then the first and second structures are bonded together so that the die becomes disposed in the first structure's cavity, and the holes of the two structures are aligned to electrically connect the respective capacitors to each other. A filler is injected into the cavity through one or more channels in the substrate of the first structure. Other embodiments are also provided.
Public/Granted literature
- US20190172903A1 MAKING ELECTRICAL COMPONENTS IN HANDLE WAFERS OF INTEGRATED CIRCUIT PACKAGES Public/Granted day:2019-06-06
Information query
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