Invention Grant
- Patent Title: Method of forming integrated circuit with gate-all-around field effect transistor and the resulting structure
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Application No.: US15867036Application Date: 2018-01-10
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Publication No.: US10431663B2Publication Date: 2019-10-01
- Inventor: Ruilong Xie , Balasubramanian Pranatharthiharan , Pietro Montanini , Julien Frougier
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Gibb & Riley, LLC
- Agent Anthony J. Canale
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/423 ; H01L27/02 ; H01L29/66 ; H01L21/306 ; H01L21/762 ; H01L21/311 ; H01L21/3105 ; H01L21/768 ; H01L21/8234 ; H01L29/06 ; H01L29/78 ; H01L29/10 ; H01L29/08 ; H01L27/088

Abstract:
Disclosed are methods for forming an integrated circuit with a nanowire-type field effect transistor and the resulting structure. A sacrificial gate is formed on a multi-layer fin. A sidewall spacer is formed with a gate section on the sacrificial gate and fin sections on exposed portions of the fin. Before or after removal of the exposed portions of the fin, the fins sections of the sidewall spacer are removed or reduced in size without exposing the sacrificial gate. Thus, the areas within which epitaxial source/drain regions are to be formed will not be bound by sidewall spacers. Furthermore, isolation material, which is deposited into these areas prior to epitaxial source/drain region formation and which is used to form isolation elements between the transistor gate and source/drain regions, can be removed without removing the isolation elements. Techniques are also disclosed for simultaneous formation of a nanosheet-type and/or fin-type field effect transistors.
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Information query
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