Invention Grant
- Patent Title: Physical vapor deposition process for semiconductor interconnection structures
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Application No.: US15880324Application Date: 2018-01-25
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Publication No.: US10438846B2Publication Date: 2019-10-08
- Inventor: Nai-Hao Yang , Hung-Wen Su , Kuan-Chia Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/28 ; H01L21/324 ; H01L21/67 ; H01L23/532 ; H01L21/285

Abstract:
The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.
Public/Granted literature
- US20190164825A1 PHYSICAL VAPOR DEPOSITION PROCESS FOR SEMICONDUCTOR INTERCONNECTION STRUCTURES Public/Granted day:2019-05-30
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