Invention Grant
- Patent Title: Top plate sampling circuit including input-dependent dual clock boost circuits
-
Application No.: US16104978Application Date: 2018-08-20
-
Publication No.: US10439628B2Publication Date: 2019-10-08
- Inventor: Ani Xavier , Neeraj Shrivastava , Arun Mohan
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Charles A. Brill; Frank D. Cimino
- Main IPC: H03M1/10
- IPC: H03M1/10 ; H03M1/12 ; G06F1/04

Abstract:
In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.
Public/Granted literature
- US20190207617A1 Top Plate Sampling Circuit Including Input-Dependent Dual Clock Boost Circuits Public/Granted day:2019-07-04
Information query