公开(公告)号：US09722622B2

公开(公告)日：2017-08-01

申请号：US15136368

申请日：2016-04-22

Applicant: Texas Instruments Incorporated

Inventor： Gehesh Edakkuttathil Muhammed ,  Naveen KV ,  Arun Mohan ,  Shagun Dusad

IPC: H03M1/12 ,  H01L23/522 ,  H01L27/08 ,  H01G4/30 ,  H03M1/80 ,  H01G4/38 ,  H01L49/02

CPC classification number: H03M1/12 ,  H01G4/30 ,  H01G4/38 ,  H01G4/385 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/90 ,  H03M1/804

Abstract: The disclosure provides a capacitor array. The capacitor array includes one or more first metal plates vertically stacked parallel to each other. A second metal plate is horizontally stacked to couple one end of each first metal plate of the one or more first metal plates. One or more third metal plates are vertically stacked parallel to the one or more first metal plates. Each third metal plate of the one or more third metal plates is stacked between two first metal plates.

公开(公告)号：US20220182266A1

公开(公告)日：2022-06-09

申请号：US17363855

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Ani Xavier ,  Jagannathan Venkataraman ,  Nagalinga Swamy Basayya Aremallapur ,  Aviral Singhal ,  Arun Mohan ,  Rakesh Chikkanayakanahalli Manjunath ,  Aravind Ganesan ,  Harshavardhan Adepu

IPC: H04L25/06 ,  H04L25/02 ,  H04L25/03

Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.

公开(公告)号：US10686461B1

公开(公告)日：2020-06-16

申请号：US16234685

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya KrishnaSwamy Nurani ,  Arun Mohan ,  Shagun Dusad ,  Neeraj Shrivastava

IPC: H03M1/06 ,  H03F1/32 ,  H03F3/45 ,  H04B1/38

Abstract: A top-plate sampling analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue amplifier coupled to the first ADC stage. The residue amplifier comprises a first transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a second transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a linearity adjustment circuit coupled to a second current terminal of at least one of the first transistor and the second transistor. The linearity adjustment circuit comprises at least one switch that changes its state as a function of an input sampling phase and a gain phase of the residue amplifier.

公开(公告)号：US10439628B2

公开(公告)日：2019-10-08

申请号：US16104978

申请日：2018-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ani Xavier ,  Neeraj Shrivastava ,  Arun Mohan

IPC: H03M1/10 ,  H03M1/12 ,  G06F1/04

Abstract: In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

公开(公告)号：US11469928B2

公开(公告)日：2022-10-11

申请号：US17363855

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Ani Xavier ,  Jagannathan Venkataraman ,  Nagalinga Swamy Basayya Aremallapur ,  Aviral Singhal ,  Arun Mohan ,  Rakesh Chikkanayakanahalli Manjunath ,  Aravind Ganesan ,  Harshavardhan Adepu

IPC: H04L25/06 ,  H04L25/03 ,  H04L25/02

Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.

公开(公告)号：US10425042B2

公开(公告)日：2019-09-24

申请号：US15859431

申请日：2017-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ani Xavier ,  Neeraj Shrivastava ,  Arun Mohan ,  Shagun Dusad

IPC: H03F3/45 ,  H03F1/30 ,  H03F1/02

Abstract: In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.

公开(公告)号：US10084466B1

公开(公告)日：2018-09-25

申请号：US15856185

申请日：2017-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ani Xavier ,  Neeraj Shrivastava ,  Arun Mohan

IPC: H03M1/10 ,  H03M1/12 ,  G06F1/04

CPC classification number: H03M1/1245 ,  G06F1/04 ,  G11C27/02

Abstract: In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.