公开(公告)号：US20230054834A1

公开(公告)日：2023-02-23

申请号：US17567775

申请日：2022-01-03

Applicant: Texas Instruments Incorporated

Inventor： Rakesh Manjunath ,  Aravind Ganesan ,  Ani Xavier ,  Jagannathan Venkataraman ,  Abhishek Agrawal ,  Charls Babu ,  Aditya Kumar

IPC: H04L27/01 ,  H04L27/20

Abstract: A signal transmission system includes an equalization filter configured to filter an input signal based at least in part on a feedback signal, a slicer configured to generate data based on the filtered input signal at a plurality of different phases, a synchronizer configured to compute a phase delay between the input signal at each of the different phases and the data, and a pattern generator configured to generate the feedback signal at a phase adjusted by the phase delay.

公开(公告)号：US11416021B2

公开(公告)日：2022-08-16

申请号：US17245711

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Ani Xavier ,  Jagannathan Venkataraman ,  Raviteja Velisetti

IPC: G06F1/10 ,  H03L7/081 ,  H03K19/20

Abstract: A first logic gate has a first input coupled to a first circuit input or a second circuit input, a second input selectively coupled to a third circuit input or a fourth circuit input, and a first output. The first output has a signal with a duty cycle that is a function of a phase difference between a first signal on the first input and a second signal on the second input. A second logic gate has a third input coupled to the third circuit input or the fourth circuit input, a fourth input coupled to the second circuit input or the fourth circuit input, and a second output. The second output has a signal with a duty cycle that is a function of a phase difference between a third signal on the third input and a fourth signal on the fourth input.

公开(公告)号：US20220182266A1

公开(公告)日：2022-06-09

申请号：US17363855

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Ani Xavier ,  Jagannathan Venkataraman ,  Nagalinga Swamy Basayya Aremallapur ,  Aviral Singhal ,  Arun Mohan ,  Rakesh Chikkanayakanahalli Manjunath ,  Aravind Ganesan ,  Harshavardhan Adepu

IPC: H04L25/06 ,  H04L25/02 ,  H04L25/03

Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.

公开(公告)号：US11855816B2

公开(公告)日：2023-12-26

申请号：US17567775

申请日：2022-01-03

Applicant: Texas Instruments Incorporated

Inventor： Rakesh Manjunath ,  Aravind Ganesan ,  Ani Xavier ,  Jagannathan Venkataraman ,  Abhishek Agrawal ,  Charls Babu ,  Aditya Kumar

IPC: H04L27/01 ,  H04L27/20

CPC classification number: H04L27/01 ,  H04L27/20

Abstract: A signal transmission system includes an equalization filter configured to filter an input signal based at least in part on a feedback signal, a slicer configured to generate data based on the filtered input signal at a plurality of different phases, a synchronizer configured to compute a phase delay between the input signal at each of the different phases and the data, and a pattern generator configured to generate the feedback signal at a phase adjusted by the phase delay.

公开(公告)号：US10439628B2

公开(公告)日：2019-10-08

申请号：US16104978

申请日：2018-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ani Xavier ,  Neeraj Shrivastava ,  Arun Mohan

IPC: H03M1/10 ,  H03M1/12 ,  G06F1/04

Abstract: In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

公开(公告)号：US10320405B2

公开(公告)日：2019-06-11

申请号：US15909378

申请日：2018-03-01

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Visvesvaraya Pentakota Appala ,  Shagun Dusad ,  Neeraj Shrivastava ,  Viswanathan Nagarajan ,  Ani Xavier ,  Rishi Soundararajan ,  Sai Aditya Nurani ,  Roswald Francis

IPC: H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/10 ,  H03M1/16 ,  H03M1/36

Abstract: In described examples, an analog to digital converter (ADC) includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

公开(公告)号：US20240259175A1

公开(公告)日：2024-08-01

申请号：US18629247

申请日：2024-04-08

Applicant: Texas Instruments Incorporated

Inventor： Ani Xavier ,  Jagannathan Venkataraman

IPC: H04L7/00

CPC classification number: H04L7/0008

Abstract: An example system includes: interleaving circuitry including a data input, a plurality of data outputs, and a plurality of clock inputs, the data input coupled to the received data input and each of the plurality of clock inputs coupled to one of the plurality of receiver clock outputs; and handoff circuitry coupled to the interleaving circuitry, the handoff circuitry including: comparison circuitry coupled to the clock generation circuitry and configured to compare the plurality of receiver clocks to the transmission clock; clock configuration circuitry coupled to the comparison circuitry and configured to select one of the plurality of receiver clocks based on the comparison circuitry; and a plurality of flip-flops coupled to the clock configuration circuitry and configured to convert the plurality of data outputs from the plurality of receiver clocks to the transmission clock to generate a plurality of transmission data streams based on the one of the plurality of receiver clocks selected by the clock configuration circuitry.

公开(公告)号：US20240030926A1

公开(公告)日：2024-01-25

申请号：US17873129

申请日：2022-07-25

Applicant: Texas Instruments Incorporated

Inventor： Ani Xavier ,  Jagannathan Venkataraman

IPC: H03L7/085 ,  H03L7/083 ,  H03L7/107 ,  H03L7/08

CPC classification number: H03L7/085 ,  H03L7/083 ,  H03L7/1072 ,  H03L7/0807

Abstract: In described examples, a retimer includes a reference voltage generator, first, second, third, and fourth comparators, a hit sensor, a window results comparison circuit, and a window control circuit. First inputs of the first, second, third, and fourth comparators receive samples of a data stream. First, second, third, and fourth outputs of the reference voltage generator are coupled to respective second inputs of the first, second, third, and fourth comparators. The third and fourth comparators output to, respectively, first and second inputs of the hit sensor. The hit sensor outputs to an input of the window results comparison circuit. The window results comparison circuit outputs to an input of the window control circuit. The window control circuit outputs to an input of the reference voltage generator.

公开(公告)号：US11063793B1

公开(公告)日：2021-07-13

申请号：US16876308

申请日：2020-05-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ani Xavier ,  Jagannathan Venkataraman ,  Sandeep Oswal

IPC: H04L27/01 ,  H04L25/03

Abstract: An equalization circuit includes a feed-forward equalization (FFE) circuit and a decision feedback equalization (DFE) circuit. The FFE circuit includes a first FFE tap, a second FFE tap coupled to the first FFE tap, and a variable gain amplifier. The variable gain amplifier includes an input and a programmable capacitor. The input is coupled to the first FFE tap and the second FFE tap. The programmable capacitor is coupled to the input. The DFE circuit includes an input and a DFE tap. The input is coupled to the variable gain amplifier. The DFE tap is coupled to the input of the variable gain amplifier.

公开(公告)号：US11956340B1

公开(公告)日：2024-04-09

申请号：US17956487

申请日：2022-09-29

Applicant: Texas Instruments Incorporated

Inventor： Ani Xavier ,  Jagannathan Venkataraman

IPC: H04L7/00

CPC classification number: H04L7/0008

Abstract: An example system includes: interleaving circuitry including a data input, a plurality of data outputs, and a plurality of clock inputs, the data input coupled to the received data input and each of the plurality of clock inputs coupled to one of the plurality of receiver clock outputs; and handoff circuitry coupled to the interleaving circuitry, the handoff circuitry including: comparison circuitry coupled to the clock generation circuitry and configured to compare the plurality of receiver clocks to the transmission clock; clock configuration circuitry coupled to the comparison circuitry and configured to select one of the plurality of receiver clocks based on the comparison circuitry; and a plurality of flip-flops coupled to the clock configuration circuitry and configured to convert the plurality of data outputs from the plurality of receiver clocks to the transmission clock to generate a plurality of transmission data streams based on the one of the plurality of receiver clocks selected by the clock configuration circuitry.