Invention Grant
- Patent Title: Method and apparatus for reducing capacitance of input/output pins of memory device
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Application No.: US15625350Application Date: 2017-06-16
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Publication No.: US10453829B2Publication Date: 2019-10-22
- Inventor: Merri Lyn Carlson , Hongbin Zhu , Gordon A. Haller , James E. Davis , Kevin G. Duesman , James Mathew , Michael P. Violette
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: H01L27/11556
- IPC: H01L27/11556 ; H01L25/10 ; H01L27/11529 ; H01L27/11548

Abstract:
In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.
Public/Granted literature
- US20180366453A1 METHOD AND APPARATUS FOR REDUCING CAPACITANCE OF INPUT/OUTPUT PINS OF MEMORY DEVICE Public/Granted day:2018-12-20
Information query
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