- Patent Title: Techniques for enhancing vertical gate-all-around FET performance
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Application No.: US15833543Application Date: 2017-12-06
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Publication No.: US10453844B2Publication Date: 2019-10-22
- Inventor: Injo Ok , Choonghyun Lee , Soon-Cheon Seo , Seyoung Kim
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Michael J. Chang, LLC
- Agent Vazken Alexanian
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/78 ; H01L29/51 ; H01L21/8238

Abstract:
Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques.
Public/Granted literature
- US20190172830A1 Techniques for Enhancing Vertical Gate-All-Around FET Performance Public/Granted day:2019-06-06
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