Invention Grant
- Patent Title: Integrating MEMS structures with interconnects and vias
-
Application No.: US15573342Application Date: 2015-06-22
-
Publication No.: US10457548B2Publication Date: 2019-10-29
- Inventor: Kevin Lai Lin , Chytra Pawashe , Raseong Kim , Ian A. Young , Kanwal Jit Singh , Robert L. Bristol
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2015/037024 WO 20150622
- International Announcement: WO2016/209207 WO 20161229
- Main IPC: B81B7/00
- IPC: B81B7/00 ; B81C1/00 ; H01L21/768

Abstract:
A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.
Public/Granted literature
- US20180086627A1 INTEGRATING MEMS STRUCTURES WITH INTERCONNECTS AND VIAS Public/Granted day:2018-03-29
Information query