Invention Grant
- Patent Title: Method for fabricating a row of MOS transistors
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Application No.: US15942540Application Date: 2018-04-01
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Publication No.: US10468306B2Publication Date: 2019-11-05
- Inventor: Loic Gaben
- Applicant: STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Crowe & Dunlevy
- Priority: FR1752859 20170403
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/02 ; H01L23/52 ; H01L27/088 ; H01L21/48 ; H01L29/66 ; H01L27/092 ; H01L29/775 ; B82Y10/00 ; H01L29/06 ; B82Y40/00 ; H01L21/311
Abstract:
A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.
Public/Granted literature
- US20180286763A1 METHOD FOR FABRICATING A ROW OF MOS TRANSISTORS Public/Granted day:2018-10-04
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