Invention Grant
- Patent Title: Systems, methods and devices for using thermal margin of a core in a processor
-
Application No.: US15086456Application Date: 2016-03-31
-
Publication No.: US10474208B2Publication Date: 2019-11-12
- Inventor: Daniel G. Cartagena , Corey D. Gough , Vivek Garg , Nikhil Gupta
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Stoel Rives LLP
- Main IPC: G06F1/20
- IPC: G06F1/20 ; G06F1/32 ; G06F1/3206 ; G06F1/324 ; G06F1/3296

Abstract:
A dynamic adjustment of core power can reduce thermal margin between thermal design power (TDP) and an allowable thermal load. For example, by focusing directly on the core temperatures explicitly, a per-core closed loop temperature controller (pCLTC) can remove conservatism induced by the power level 1 policy (PL1, a policy which defines frequency and/or power for the processor under sustained load) thereby allowing for increased processor performance when there exists margin in the thermal system.
Public/Granted literature
- US20170285700A1 SYSTEMS, METHODS AND DEVICES FOR USING THERMAL MARGIN OF A CORE IN A PROCESSOR Public/Granted day:2017-10-05
Information query