Invention Grant
- Patent Title: Transistor device structures with retrograde wells in CMOS applications
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Application No.: US15792357Application Date: 2017-10-24
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Publication No.: US10483172B2Publication Date: 2019-11-19
- Inventor: Vara G. Reddy Vakada , Laegu Kang , Michael Ganz , Yi Qi , Puneet Khanna , Srikanth Balaji Samavedam , Sri Charan Vemula , Manfred Eller
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L21/82
- IPC: H01L21/82 ; H01L27/092 ; H01L21/8238

Abstract:
A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.
Public/Granted literature
- US20180047641A1 TRANSISTOR DEVICE STRUCTURES WITH RETROGRADE WELLS IN CMOS APPLICATIONS Public/Granted day:2018-02-15
Information query
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