公开(公告)号：US09966313B2

公开(公告)日：2018-05-08

申请号：US15229431

申请日：2016-08-05

申请人： GLOBALFOUNDRIES Inc.

发明人： Shesh Mani Pandey ,  Baofu Zhu ,  Srikanth Balaji Samavedam

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/823481 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/66818 ,  H01L29/7853

摘要： A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.

公开(公告)号：US09576952B2

公开(公告)日：2017-02-21

申请号：US14188778

申请日：2014-02-25

申请人： GLOBALFOUNDRIES Inc.

发明人： Manoj Joshi ,  Manfred Eller ,  Richard J. Carter ,  Srikanth Balaji Samavedam

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0922 ,  H01L27/0924

摘要： Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).

摘要翻译： 提供集成电路和制造方法。 集成电路包括：设置在衬底结构上的变化的栅极结构，所述变化的栅极结构包括在衬底结构的第一区域中的第一栅极堆叠，以及在衬底结构的第二区域中的第二栅极堆叠; 所述第一区域中的第一场效应晶体管，所述第一场效应晶体管包括所述第一栅极叠层并具有第一阈值电压; 以及第二区域中的第二场效应晶体管，所述第二场效应晶体管包括所述第二栅极堆叠并且具有第二阈值电压，其中所述第一阈值电压不同于所述第二阈值电压。 所述方法包括提供变化的栅极结构，所述提供包括：具有不同厚度（es）的不同栅极结构的尺寸层。

公开(公告)号：US20160035630A1

公开(公告)日：2016-02-04

申请号：US14882640

申请日：2015-10-14

申请人： GLOBALFOUNDRIES Inc.

发明人： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

摘要： One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region.

摘要翻译： 本文公开的一种说明性方法包括执行第一多个外延沉积工艺，以在掩蔽P活性区域的同时，选择性地在N活性区域上方形成第一多个半导体材料，进行第二多个外延沉积工艺以形成第二多个 半导体材料选择性地在P有源区上方，同时掩蔽N有源区，在N-有源区中和上方形成N型晶体管，并在P-活性区中和上方形成P型晶体管。

公开(公告)号：US09935112B1

公开(公告)日：2018-04-03

申请号：US15599581

申请日：2017-05-19

申请人： GLOBALFOUNDRIES Inc.

发明人： Hui Zang ,  Srikanth Balaji Samavedam

IPC分类号： H01L27/11 ,  H01L27/088

CPC分类号： H01L27/1104 ,  G11C8/16 ,  G11C11/412 ,  H01L27/0207 ,  H01L29/786

摘要： A static random access memory (SRAM) cell includes 1st and 2nd fins disposed on a substrate. A 1st pass gate transistor (1st PG) is embedded in the 1st fin. The 1st PG has a source region and a drain region disposed over the 1st and 2nd fins. A 1st gate structure (1st PG-G) is disposed over the 1st fin and between the source and drain regions. The 1st PG-G is electrically connected to a 1st word line. A 2nd pass gate transistor (2nd PG) is embedded in the 2nd fin. The 2nd PG has the same source and drain regions. A 2nd gate structure (2nd PG-G) is disposed over the 2nd fin and between the source and drain regions. The 2nd PG-G is electrically connected to a 2nd word line. A 1st CT pillar is disposed between the 1st PG-G and 2nd PG-G.

公开(公告)号：US09508743B2

公开(公告)日：2016-11-29

申请号：US14525842

申请日：2014-10-28

申请人： GLOBALFOUNDRIES Inc.

发明人： Jagar Singh ,  Srikanth Balaji Samavedam

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L29/06 ,  H01L23/66 ,  H01L21/762 ,  H01L27/092

CPC分类号： H01L27/1211 ,  H01L21/76229 ,  H01L21/7624 ,  H01L21/845 ,  H01L23/66 ,  H01L27/092 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

摘要： Co-fabrication of a radio-frequency (RF) semiconductor device with a three-dimensional semiconductor device includes providing a starting three-dimensional semiconductor structure, the starting structure including a bulk silicon semiconductor substrate, raised semiconductor structure(s) coupled to the substrate and surrounded by a layer of isolation material. Span(s) of the layer of isolation material between adjacent raised structures are recessed, and a layer of epitaxial semiconductor material is created over the recessed span(s) of isolation material over which another layer of isolation material is created. The RF device(s) are fabricated on the layer of isolation material above the epitaxial material, which creates a local silicon-on-insulator, while the three-dimensional semiconductor device(s) can be fabricated on the raised structure(s).

摘要翻译： 具有三维半导体器件的射频（RF）半导体器件的共同制造包括提供起始三维半导体结构，起始结构包括体硅半导体衬底，耦合到衬底的凸起半导体结构 并被一层隔离材料包围。 在相邻的凸起结构之间的隔离材料层的跨度是凹进的，并且在隔离材料的凹陷跨度上形成一层外延半导体材料，在其上产生另一层隔离材料。 RF器件制造在外延材料上方的隔离材料层上，其产生局部绝缘体上硅，而三维半导体器件可以在凸起结构上制造。

公开(公告)号：US09209181B2

公开(公告)日：2015-12-08

申请号：US13918536

申请日：2013-06-14

申请人： GLOBALFOUNDRIES Inc.

发明人： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

摘要： A method includes forming a layer of silicon-carbon on an N-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon and on the P-active region, masking the N-active region, forming a layer of a second semiconductor material on the first semiconductor material in the P-active region and forming N-type and P-type transistors. A device includes a layer of silicon-carbon positioned on an N-active region, a first layer of a first semiconductor positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on a P-active region, a layer of a second semiconductor material positioned on the second layer of the first semiconductor material, and N-type and P-type transistors.

摘要翻译： 一种方法包括在N-有源区上形成一层硅 - 碳，进行公共沉积工艺，以在硅 - 碳层和P-活性区上形成第一半导体材料层， 在P活性区域中的第一半导体材料上形成第二半导体材料层，形成N型和P型晶体管。 一种器件包括位于N-有源区上的硅碳层，位于硅碳层上的第一半导体的第一层，位于P活性区上的第一半导体材料的第二层， 位于第一半导体材料的第二层上的第二半导体材料的层，以及N型和P型晶体管。

公开(公告)号：US20200273953A1

公开(公告)日：2020-08-27

申请号：US16287365

申请日：2019-02-27

申请人： GLOBALFOUNDRIES Inc.

发明人： Tao Chu ,  Wei Ma ,  Jae Gon Lee ,  Hong Yu ,  Zhenyu Hu ,  Srikanth Balaji Samavedam

IPC分类号： H01L29/10 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

摘要： One illustrative integrated circuit product disclosed herein includes a short-channel transistor device and a long-channel transistor device formed above a semiconductor substrate, wherein a first gate structure for the short-channel transistor device includes a short-channel WFM layer with a first upper surface that is positioned at a first distance above an upper surface of the semiconductor substrate, and wherein a second gate structure for the long-channel transistor device includes a long-channel WFM layer with a second upper surface that is positioned at a second distance above the upper surface of the semiconductor substrate, wherein the first distance is greater than the second distance.

公开(公告)号：US20200044069A1

公开(公告)日：2020-02-06

申请号：US16049849

申请日：2018-07-31

申请人： GLOBALFOUNDRIES INC.

发明人： Julien Frougier ,  Ruilong Xie ,  Andreas Knorr ,  Srikanth Balaji Samavedam

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/762

摘要： Disclosed are methods of forming a semiconductor structure including a bulk semiconductor substrate and, on the substrate, a fin-type field effect transistor (FINFET) with a uniform channel length and a below-channel buried insulator. In the methods, a semiconductor fin is formed with a sacrificial semiconductor layer between lower and upper semiconductor layers. During processing, the sacrificial semiconductor layer is replaced with dielectric spacer material (i.e., a buried insulator). The buried insulator functions as an etch stop layer when etching source/drain recesses, ensuring that they have vertical sidewalls and, thereby ensuring that the channel region has a uniform length. The buried insulator also provides isolation between channel region and the substrate below and prevents dopant diffusion into the channel region from a punch-through stopper (if present). Optionally, the buried insulator is formed so as to contain an air-gap. Also disclosed are structures resulting from the methods.

公开(公告)号：US09362180B2

公开(公告)日：2016-06-07

申请号：US14189085

申请日：2014-02-25

申请人： GLOBALFOUNDRIES Inc.

发明人： Bongki Lee ,  Jin Ping Liu ,  Manoj Joshi ,  Manfred Eller ,  Rohit Pal ,  Richard J. Carter ,  Srikanth Balaji Samavedam

IPC分类号： H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L21/28 ,  H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

摘要： In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.

摘要翻译： 在一个方面，这里提出了具有第一多个场效应晶体管和第二多个场效应晶体管的集成电路，其中第一多个场效应晶体管的场效应晶体管各自具有第一栅极堆叠，并且其中场效应 第二多个场效应晶体管的晶体管每个都具有第二栅极堆叠，第二栅极堆叠通过具有与第一栅极堆叠共同的金属层与第一栅极堆叠而不同于第一栅极堆叠，第二栅极堆叠包括第一栅极堆叠的第一厚度 第一栅极堆叠和第二栅极堆叠处的第二厚度。

公开(公告)号：US10483172B2

公开(公告)日：2019-11-19

申请号：US15792357

申请日：2017-10-24

申请人： GLOBALFOUNDRIES Inc.

发明人： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC分类号： H01L21/82 ,  H01L27/092 ,  H01L21/8238

摘要： A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.