公开(公告)号：US10483172B2

公开(公告)日：2019-11-19

申请号：US15792357

申请日：2017-10-24

申请人： GLOBALFOUNDRIES Inc.

发明人： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC分类号： H01L21/82 ,  H01L27/092 ,  H01L21/8238

摘要： A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.

公开(公告)号：US10262903B2

公开(公告)日：2019-04-16

申请号：US15630547

申请日：2017-06-22

申请人： GLOBALFOUNDRIES INC.

发明人： Judson R. Holt ,  Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06

摘要： The present disclosure relates to semiconductor structures and, more particularly, to an N-P boundary spacer structure used with finFET devices and methods of manufacture. The method includes forming a plurality of first fin structures, forming a blocking layer between a first fin structure of the plurality of fin structures and a second fin structure of the plurality of fin structures, and forming an epitaxial material on the first fin structure, while blocking the epitaxial material from extending onto the second fin structure by at least the blocking layer formed between the first fin structure and the second fin structure.

公开(公告)号：US10170473B1

公开(公告)日：2019-01-01

申请号：US15811745

申请日：2017-11-14

申请人： GLOBALFOUNDRIES INC.

发明人： Hui Zang ,  Josef S. Watts ,  Yi Qi

IPC分类号： H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/266 ,  H01L29/66 ,  H01L29/06

摘要： A method of forming an integrated circuit includes forming a FinFET by: forming a semiconductor fin on a semiconductor substrate; forming a first source/drain region in the semiconductor substrate under a first end of the semiconductor fin and a second source/drain region in the semiconductor substrate under a second, opposing end of the semiconductor fin, the second source/drain region separated from the first source/drain region by a portion of the semiconductor substrate having an opposite doping from that of the first and second source/drain region; and forming a surrounding gate extending about the semiconductor fin above the semiconductor substrate. A second vertical FinFET may be formed simultaneously. The method allows the FinFET to have a long channel extending laterally through its fin compared to the short channel of the vertical FinFET, thus creating short channel and long channel devices together without impacting vertical FinFET height.

公开(公告)号：US09852954B2

公开(公告)日：2017-12-26

申请号：US14882640

申请日：2015-10-14

申请人： GLOBALFOUNDRIES Inc.

发明人： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

摘要： One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region.

公开(公告)号：US09524908B2

公开(公告)日：2016-12-20

申请号：US14242529

申请日：2014-04-01

申请人： GLOBALFOUNDRIES Inc.

发明人： Yi Qi ,  Ajey Poovannummoottil Jacob

IPC分类号： H01L21/308 ,  H01L21/3213 ,  H01L21/8234

CPC分类号： H01L21/823431

摘要： One illustrative method disclosed herein includes, among other things, forming a region of a sacrificial material in a semiconductor substrate at a location where the portion of the fin to be removed will be located, after forming the region of sacrificial material, performing at least one first etching process to form a plurality of fin-formation trenches that define the fin, wherein at least a portion of the fin is comprised of the sacrificial material, and performing at least one second etching process to selectively remove substantially all of the sacrificial material portion of the fin relative to the substrate.

摘要翻译： 本文中公开的一种说明性方法包括在形成牺牲材料区域之后，在要被去除的翅片的部分将被定位的位置处在半导体衬底中形成牺牲材料的区域，执行至少一个 第一蚀刻工艺以形成限定翅片的多个翅片形成沟槽，其中鳍片的至少一部分由牺牲材料构成，并且执行至少一个第二蚀刻工艺以选择性地移除基本上所有的牺牲材料部分 的翅片相对于基底。

公开(公告)号：US09490123B2

公开(公告)日：2016-11-08

申请号：US14523334

申请日：2014-10-24

申请人： GLOBALFOUNDRIES Inc.

发明人： Yi Qi ,  David Paul Brunco

IPC分类号： H01L21/20 ,  H01L21/70 ,  H01L21/762 ,  H01L21/36 ,  H01L21/302 ,  H01L21/461 ,  H01L21/02

CPC分类号： H01L21/02664 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02694

摘要： One illustrative method disclosed herein includes, among other things, sequentially forming a first material layer, a first capping layer, a second material layer and a second capping layer above a substrate, wherein the first and second material layers are made of semiconductor material having a lattice constant that is different than the substrate, the first material layer is strained as deposited, and a thickness of the first material layer exceeds its critical thickness required to be stable and strained, performing an anneal process after which the strain in the first material layer is substantially relaxed through the formation of crystallographic defects that are substantially confined to the semiconducting substrate, the first material layer, the first capping layer and the second material layer, and forming additional epitaxial semiconductor material on an upper surface of the resulting structure.

摘要翻译： 本文公开的一种说明性方法包括在衬底上顺序地形成第一材料层，第一覆盖层，第二材料层和第二覆盖层，其中第一和第二材料层由半导体材料制成，其具有 晶格常数不同于衬底，第一材料层被应变成沉积，并且第一材料层的厚度超过其要求稳定和应变的临界厚度，进行退火工艺，之后第一材料层中的应变 通过形成基本上限制于半导体衬底，第一材料层，第一覆盖层和第二材料层的晶体缺陷，以及在所得结构的上表面上形成附加的外延半导体材料而基本上松弛。

公开(公告)号：US09397200B2

公开(公告)日：2016-07-19

申请号：US14867800

申请日：2015-09-28

申请人： GLOBALFOUNDRIES Inc.

发明人： Yi Qi

IPC分类号： H01L27/01 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/66553 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78696

摘要： One illustrative method involves forming a FinFET device or a nanowire device by forming a sacrificial gate structure above a substantially vertically oriented structure comprised of first and second semiconductor materials, forming epi semiconductor material in the source/drain regions, removing the sacrificial gate structure so as to define a replacement gate cavity and to expose the first and second semiconductor materials within the gate cavity, performing an etching process through the replacement gate cavity to selectively remove the exposed first sacrificial semiconductor material relative to the exposed second semiconductor material so as to define a gap under the second semiconductor material within the gate cavity, filling the gap with an insulating material, and forming a replacement gate structure in the gate cavity.

摘要翻译： 一种说明性方法包括通过在由第一和第二半导体材料构成的基本垂直取向的结构上方形成牺牲栅极结构，形成FinFET器件或纳米线器件，在源极/漏极区域形成外延半导体材料，去除牺牲栅极结构，以便 以限定替换栅极腔并且暴露栅极腔内的第一和第二半导体材料，通过替代栅极腔执行蚀刻工艺，以相对于暴露的第二半导体材料选择性地去除暴露的第一牺牲半导体材料，以便限定 在栅腔内的第二半导体材料下面的间隙，用绝缘材料填充间隙，并在栅腔中形成替换栅极结构。

公开(公告)号：US20160118255A1

公开(公告)日：2016-04-28

申请号：US14523334

申请日：2014-10-24

申请人： GLOBALFOUNDRIES Inc.

发明人： Yi Qi ,  David Paul Brunco

IPC分类号： H01L21/02

CPC分类号： H01L21/02664 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02694

摘要： One illustrative method disclosed herein includes, among other things, sequentially forming a first material layer, a first capping layer, a second material layer and a second capping layer above a substrate, wherein the first and second material layers are made of semiconductor material having a lattice constant that is different than the substrate, the first material layer is strained as deposited, and a thickness of the first material layer exceeds its critical thickness required to be stable and strained, performing an anneal process after which the strain in the first material layer is substantially relaxed through the formation of crystallographic defects that are substantially confined to the semiconducting substrate, the first material layer, the first capping layer and the second material layer, and forming additional epitaxial semiconductor material on an upper surface of the resulting structure.

摘要翻译： 本文公开的一种说明性方法包括在衬底上顺序地形成第一材料层，第一覆盖层，第二材料层和第二覆盖层，其中第一和第二材料层由半导体材料制成，其具有 晶格常数不同于衬底，第一材料层被应变成沉积，并且第一材料层的厚度超过其要求稳定和应变的临界厚度，进行退火工艺，之后第一材料层中的应变 通过形成基本上限制于半导体衬底，第一材料层，第一覆盖层和第二材料层的晶体缺陷，以及在所得结构的上表面上形成附加的外延半导体材料而基本上松弛。

公开(公告)号：US20140367787A1

公开(公告)日：2014-12-18

申请号：US13918536

申请日：2013-06-14

申请人： GLOBALFOUNDRIES Inc.

发明人： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC分类号： H01L27/092 ,  H01L21/8234

CPC分类号： H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

摘要： A method includes forming a layer of silicon-carbon on an N-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon and on the P-active region, masking the N-active region, forming a layer of a second semiconductor material on the first semiconductor material in the P-active region and forming N-type and P-type transistors. A device includes a layer of silicon-carbon positioned on an N-active region, a first layer of a first semiconductor positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on a P-active region, a layer of a second semiconductor material positioned on the second layer of the first semiconductor material, and N-type and P-type transistors.

摘要翻译： 一种方法包括在N-有源区上形成一层硅 - 碳，进行公共沉积工艺，以在硅 - 碳层和P-活性区上形成第一半导体材料层， 在P活性区域中的第一半导体材料上形成第二半导体材料层，形成N型和P型晶体管。 一种器件包括位于N-有源区上的硅碳层，位于硅碳层上的第一半导体的第一层，位于P活性区上的第一半导体材料的第二层， 位于第一半导体材料的第二层上的第二半导体材料的层，以及N型和P型晶体管。

公开(公告)号：US10559656B2

公开(公告)日：2020-02-11

申请号：US15968968

申请日：2018-05-02

申请人： GLOBALFOUNDRIES INC.

发明人： Emilie M. S. Bourjot ,  Julien Frougier ,  Yi Qi ,  Ruilong Xie ,  Hui Zang ,  Hsien-Ching Lo ,  Zhenyu Hu

IPC分类号： H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/285

摘要： Described herein are nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects described include nanosheet-FET structures having an air gap as a bottom isolation area to reduce parasitic S/D leakage to the substrate.