Invention Grant
- Patent Title: Method for coloring circuit layout and system for performing the same
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Application No.: US15718522Application Date: 2017-09-28
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Publication No.: US10509881B2Publication Date: 2019-12-17
- Inventor: Chia-Ping Chiang , Ming-Hui Chih , Chih-Wei Hsu , Ping-Chieh Wu , Ya-Ting Chang , Tsung-Yu Wang , Wen-Li Cheng , Hui En Yin , Wen-Chun Huang , Ru-Gun Liu , Tsai-Sheng Gau
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G03F1/70 ; G03F7/20

Abstract:
Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
Public/Granted literature
- US20190095569A1 METHOD FOR COLORING CIRCUIT LAYOUT AND SYSTEM FOR PERFORMING THE SAME Public/Granted day:2019-03-28
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