公开(公告)号：US10509881B2

公开(公告)日：2019-12-17

申请号：US15718522

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ping Chiang ,  Ming-Hui Chih ,  Chih-Wei Hsu ,  Ping-Chieh Wu ,  Ya-Ting Chang ,  Tsung-Yu Wang ,  Wen-Li Cheng ,  Hui En Yin ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: G06F17/50 ,  G03F1/70 ,  G03F7/20

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

公开(公告)号：US09911606B2

公开(公告)日：2018-03-06

申请号：US15267341

申请日：2016-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ping Chiang ,  Ya-Ting Chang ,  Wen-Li Cheng ,  Nian-Fuh Cheng ,  Ming-Hui Chih ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: H01L21/311 ,  H01L21/033 ,  G03F7/20 ,  H01L21/768 ,  H01L31/18

CPC classification number: G03F7/70283 ,  G03F1/70 ,  G06F17/5081 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76831 ,  H01L21/76843 ,  H01L31/1892

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a design layout of the IC, wherein the design layout includes two abutting blocks, the two blocks include target patterns, and the target patterns have different pitches in the two blocks. The method further includes generating mandrel pattern candidates in spaces between adjacent target patterns, and assigning first and second colors to the mandrel pattern candidates according to their priorities. The method further includes removing the mandrel pattern candidates assigned with the second color, and outputting a mandrel pattern in computer-readable format for mask fabrication. The mandrel pattern includes the mandrel pattern candidates that are colored with the first color.

公开(公告)号：US20170316938A1

公开(公告)日：2017-11-02

申请号：US15267341

申请日：2016-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ping Chiang ,  Ya-Ting Chang ,  Wen-Li Cheng ,  Nian-Fuh Cheng ,  Ming-Hui Chih ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: H01L21/033 ,  G03F7/20

CPC classification number: G03F7/70283 ,  G03F1/70 ,  G06F17/5081 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76831 ,  H01L21/76843 ,  H01L31/1892

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a design layout of the IC, wherein the design layout includes two abutting blocks, the two blocks include target patterns, and the target patterns have different pitches in the two blocks. The method further includes generating mandrel pattern candidates in spaces between adjacent target patterns, and assigning first and second colors to the mandrel pattern candidates according to their priorities. The method further includes removing the mandrel pattern candidates assigned with the second color, and outputting a mandrel pattern in computer-readable format for mask fabrication. The mandrel pattern includes the mandrel pattern candidates that are colored with the first color.

公开(公告)号：US10796055B2

公开(公告)日：2020-10-06

申请号：US16660506

申请日：2019-10-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ping Chiang ,  Ming-Hui Chih ,  Chih-Wei Hsu ,  Ping-Chieh Wu ,  Ya-Ting Chang ,  Tsung-Yu Wang ,  Wen-Li Cheng ,  Hui En Yin ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: G06F30/39 ,  G03F1/70 ,  G03F7/20

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.