中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.03 seconds)

    Methodology for pattern correction
    1.
    发明授权
    Methodology for pattern correction 有权
    模式校正方法

    公开(公告)号：US09026955B1

    公开(公告)日：2015-05-05

    申请号：US14051568

    申请日：2013-10-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Feng-Ju Chang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50

    CPC classification number: G03F1/36 ,  G03F7/70433 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.

    Abstract translation: 本公开涉及通过分开校正IC设计的主要特征形状和虚拟形状以及相关联的装置来减少图案校正周期时间的集成芯片（IC）设计图案校正的方法。 在一些实施例中，通过形成具有多个主要特征形状的IC设计来执行该方法。 将多个虚拟形状添加到IC设计中以改善IC设计的处理窗口。 使用第一图案校正处理来校正多个主要特征形状。 随后使用与第一图案校正处理分开的第二图案校正处理来校正多个虚拟形状中的一个或多个。 通过单独地校正虚拟形状和主要特征形状，可以对虚拟形状进行具有较低时间/资源需求的不同的图案校正处理，从而减少图案校正周期时间。

    METHODOLOGY FOR PATTERN DENSITY OPTIMIZATION
    4.
    发明申请
    METHODOLOGY FOR PATTERN DENSITY OPTIMIZATION 审中-公开
    模式密度优化方法

    公开(公告)号：US20160275232A1

    公开(公告)日：2016-09-22

    申请号：US15170026

    申请日：2016-06-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Wen-Hao Liu ,  Cheng-Hsuan Huang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50 ,  G03F1/36

    CPC classification number: G06F17/5081 ,  G03F1/36

    Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.

    Abstract translation: 本公开涉及一种利用低OPC（光学邻近校正）周期时间改进图案密度的方法，以及相关联的装置。 在一些实施例中，通过对包括用于制造集成芯片的布局的图形表示的IC设计执行初始数据准备处理来执行该方法。 通过使用数据准备元件来进行初始数据准备处理，以生成具有改进形状的修改的IC设计，其是IC设计中的形状的修改形式。 使用局部密度检查元件来识别修改的IC设计的一个或多个低图案密度区域。 使用虚拟形状插入元件在一个或多个低图案密度区域内添加一个或多个虚拟形状。 一个或多个虚拟形状通过非零空间与修改后的形状分离。

    METHODOLOGY FOR PATTERN DENSITY OPTIMIZATION
    8.
    发明申请
    METHODOLOGY FOR PATTERN DENSITY OPTIMIZATION 有权
    模式密度优化方法

    公开(公告)号：US20150106779A1

    公开(公告)日：2015-04-16

    申请号：US14051549

    申请日：2013-10-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Wen-Hao Liu ,  Cheng-Hsuan Huang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F1/36

    Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.

    Abstract translation: 本公开涉及一种利用低OPC（光学邻近校正）周期时间改进图案密度的方法，以及相关联的装置。 在一些实施例中，该方法通过形成作为集成芯片的图形表示的集成芯片（IC）设计来执行。 识别IC设计中的一个或多个低图案密度区域具有导致处理失败的图案密度。 低图案密度区域是IC设计的一个子集。 通过在低图案密度区域内添加一个或多个虚拟形状，在低图案密度区域内调整图案密度。 然后对IC设计执行数据准备处理，以修改低图案密度区域内的一个或多个虚拟形状的形状。 通过将虚拟形状引入局部区域而不是整个集成芯片设计中，随后的数据准备过程的需求减少。

    METHODOLOGY FOR PATTERN CORRECTION
    9.
    发明申请
    METHODOLOGY FOR PATTERN CORRECTION 有权
    模式校正方法

    公开(公告)号：US20150106773A1

    公开(公告)日：2015-04-16

    申请号：US14051568

    申请日：2013-10-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Feng-Ju Chang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50

    CPC classification number: G03F1/36 ,  G03F7/70433 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.

    Abstract translation: 本公开涉及通过分开校正IC设计的主要特征形状和虚拟形状以及相关联的装置来减少图案校正周期时间的集成芯片（IC）设计图案校正的方法。 在一些实施例中，通过形成具有多个主要特征形状的IC设计来执行该方法。 将多个虚拟形状添加到IC设计中以改善IC设计的处理窗口。 使用第一图案校正处理来校正多个主要特征形状。 随后使用与第一图案校正处理分开的第二图案校正处理来校正多个虚拟形状中的一个或多个。 通过单独地校正虚拟形状和主要特征形状，可以对虚拟形状进行具有较低时间/资源需求的不同的图案校正处理，从而减少图案校正周期时间。

Patent Agency Ranking