Invention Grant
- Patent Title: High voltage CMOS with co-planar upper gate surfaces for embedded non-volatile memory
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Application No.: US16396937Application Date: 2019-04-29
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Publication No.: US10535675B2Publication Date: 2020-01-14
- Inventor: Harry-Hak-Lay Chuang , Wei Cheng Wu , Ya-Chen Kao , Yi Hsien Lu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L29/792
- IPC: H01L29/792 ; H01L27/11573 ; H01L29/66 ; H01L29/423 ; H01L29/51 ; H01L21/8234 ; H01L27/092 ; H01L27/088

Abstract:
The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.
Public/Granted literature
- US20190252400A1 HKMG HIGH VOLTAGE CMOS FOR EMBEDDED NON-VOLATILE MEMORY Public/Granted day:2019-08-15
Information query
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