- Patent Title: Closely packed vertical transistors with reduced contact resistance
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Application No.: US16023244Application Date: 2018-06-29
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Publication No.: US10535755B2Publication Date: 2020-01-14
- Inventor: Zhenxing Bi , Kangguo Cheng , Juntao Li , Peng Xu
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/08 ; H01L29/78 ; H01L29/417 ; H01L21/311 ; H01L27/11582 ; H01L27/112 ; H01L21/768 ; H01L23/522 ; H01L23/485

Abstract:
A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a semiconductor structure on a doped region of a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin. A liner is formed on the gate and the semiconductor fin, and a dielectric layer is formed on the liner. Portions of the liner are removed to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer. A recessed opening is formed by recessing portions of the liner from the exposed sidewall of the dielectric layer. A top epitaxy region is formed on the exposed portions of the semiconductor fin and dielectric layer such that an extension of the top epitaxy region fills the recessed opening. The top epitaxy region is confined between portions of the liner.
Public/Granted literature
- US20180323283A1 CLOSELY PACKED VERTICAL TRANSISTORS WITH REDUCED CONTACT RESISTANCE Public/Granted day:2018-11-08
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