Invention Grant
- Patent Title: Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs
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Application No.: US16100425Application Date: 2018-08-10
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Publication No.: US10573714B2Publication Date: 2020-02-25
- Inventor: Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Xin Miao
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/06 ; H01L29/66 ; H01L29/08 ; H01L29/423 ; H01L29/10 ; H01L29/417 ; H01L29/78

Abstract:
Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.
Public/Granted literature
- US20180366544A1 SACRIFICIAL LAYER FOR CHANNEL SURFACE RETENTION AND INNER SPACER FORMATION IN STACKED-CHANNEL FETS Public/Granted day:2018-12-20
Information query
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