公开(公告)号：US11764259B2

公开(公告)日：2023-09-19

申请号：US17384307

申请日：2021-07-23

Applicant: International Business Machines Corporation

Inventor： Chen Zhang ,  Tenko Yamashita ,  Xin Miao ,  Wenyu Xu ,  Kangguo Cheng

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L29/41741 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical field-effect transistor includes a substrate comprising a semiconductor material; a first set of fins formed from the semiconductor material and extending vertically with respect to the substrate; and a second set of fins extending vertically with respect to the substrate, wherein ones of the second set of fins abut ones of the first set of fins. The second set of fins comprises a dielectric material.

公开(公告)号：US11705517B2

公开(公告)日：2023-07-18

申请号：US17136185

申请日：2020-12-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xin Miao ,  Kangguo Cheng ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/762 ,  H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L29/7843 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/0262 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116

Abstract: A method of fabricating a semiconductor device is described. The method includes forming a nanosheet stack on a substrate, the nanosheet stack includes nanosheet channel layers. A gate is formed around the nanosheet channel layers of the nanosheet stack. A strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the nanosheet channel layers of the nanosheet stack.

公开(公告)号：US20230013383A1

公开(公告)日：2023-01-19

申请号：US17376752

申请日：2021-07-15

Applicant: International Business Machines Corporation

Inventor： Xin Miao ,  Kangguo Cheng ,  Chen Zhang ,  Wenyu Xu

IPC: H01L29/78 ,  H01L29/66

Abstract: Vertical transport field-effect transistors are formed on active regions wherein the active regions each include a wrap-around metal silicide contact on vertically extending side walls of the active region. Such wrap-around contacts form self-aligned and reliable strapping for SRAM bottom nFET and pFET source/drain regions. Buried contacts of SRAM cells may be used to strap the wrap-around metal silicide contacts with the gates of inverters thereof. Wrap-around metal silicide contacts provide additional contacts for logic FETs and reduce parasitic bottom source/drain resistance.

公开(公告)号：US11502169B2

公开(公告)日：2022-11-15

申请号：US17128351

申请日：2020-12-21

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Jingyun Zhang ,  Xin Miao ,  Alexander Reznicek

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: A method of manufacturing a nanosheet field effect transistor (FET) device is provided. The method includes forming a plurality of nanosheet stacks on a substrate, the nanosheet stacks including alternating layers of first type sacrificial layers and active semiconductor layers. The method includes forming the first type sacrificial layer on sidewalls of the nanosheet stacks, then forming a dielectric pillar between the sidewall portions of the first type sacrificial layers of adjacent nanosheet stacks, and then removing the first type sacrificial layer. The method also includes forming a PWFM layer in spaces formed by the removal of the first type sacrificial layer for a first one of the nanosheet stacks, and includes forming a NWFM layer in spaces formed by the removal of the first type sacrificial layer for an adjacent second one of the nanosheet stacks.

公开(公告)号：US11251280B2

公开(公告)日：2022-02-15

申请号：US16717204

申请日：2019-12-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Chen Zhang ,  Kangguo Cheng ,  Xin Miao ,  Lan Yu

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: Forming a fin, where the fin includes a nanowire stack on a semiconductor substrate, where the nanowire stack includes a plurality of silicon layers and a plurality of silicon germanium layers stacked one on top of the other in an alternating fashion, removing a portion of the fin to form an opening and expose vertical sidewalls of the plurality of silicon layers and the plurality of silicon germanium layer, and epitaxially growing a source drain region/structure in the opening from the exposed vertical sidewalls of the plurality of silicon layers and the plurality of silicon germanium layers, where the source drain region/structure substantially fills the opening.

公开(公告)号：US11094798B2

公开(公告)日：2021-08-17

申请号：US16441640

申请日：2019-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lan Yu ,  Xin Miao ,  Chen Zhang ,  Heng Wu ,  Kangguo Cheng

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/40 ,  H01L21/324 ,  H01L29/78

Abstract: An embodiment of the invention may include a method of forming a semiconductor structure, and the resulting semiconductor structure. The method may include removing a gate region from a layered stack located on a source/drain layer. The layered stack includes a first spacer located on the source drain layer, a dummy layer located on the first spacer, and a second spacer located on the dummy layer. The method may include forming a channel material above the source/drain layer in the gate region. The method may include forming a top source/drain on the channel material. The method may include forming a hardmask surrounding the top source/drain. The method may include removing a portion of the layered stack that is not beneath the hardmask.

公开(公告)号：US11075273B1

公开(公告)日：2021-07-27

申请号：US16808504

申请日：2020-03-04

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Xin Miao ,  Choonghyun Lee ,  Jingyun Zhang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/165 ,  H01L29/167 ,  H01L21/324 ,  H01L21/02 ,  H01L21/225 ,  H01L29/36 ,  H01L27/02

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A stack of alternating nanosheets of sacrificial semiconductor material nanosheets and semiconductor material nanosheets located on a surface of a substrate are provided, wherein a sacrificial gate structure and a dielectric spacer material layer straddle over the nanosheet stack. End portions of each of the sacrificial semiconductor material nanosheets are recessed. A dielectric spacer is formed within each recess. Doped semiconductor portions are formed on the physically exposed sidewalls of each semiconductor material nanosheet and on the surface of the substrate. The semiconductor structure is thermally annealed. The sacrificial gate, each sacrificial semiconductor material nanosheet, and the dielectric spacer are each removed. A doped epitaxial material structure is formed in regions occupied by each sacrificial semiconductor material nanosheet, where the doped epitaxial material structure wraps around each suspended semiconductor material nanosheet.

公开(公告)号：US11069775B2

公开(公告)日：2021-07-20

申请号：US16690338

申请日：2019-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10 ,  H01L21/84 ,  H01L29/417 ,  H01L29/78

Abstract: Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.

公开(公告)号：US20210210637A1

公开(公告)日：2021-07-08

申请号：US16736898

申请日：2020-01-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingyun Zhang ,  Xin Miao ,  Ruilong Xie ,  Alexander Reznicek

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/66

Abstract: A method is presented for reducing sagging effects in nanosheet devices. The method includes forming at least two nanosheet structures over a substrate, wherein each nanosheet structure includes alternating layers of a first semiconductor material and a second semiconductor material, depositing a dielectric layer over the at least two nanosheet structures, depositing a dummy gate over the dielectric layer, etching the first semiconductor material to create voids filled with inner spacers, removing the dummy gate and the dielectric layer such that a supporting dielectric section remains between the at least two nanosheet structures, and removing the etched first semiconductor material such that a supporting structure is defined including the supporting dielectric section and the second semiconductor material.

公开(公告)号：US10978356B2

公开(公告)日：2021-04-13

申请号：US16408799

申请日：2019-05-10

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Xin Miao ,  Alexander Reznicek ,  Jingyun Zhang

IPC: H01L21/02 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092

Abstract: A method of forming a semiconductor structure includes forming a recess within a semiconductor substrate, the recess is located between adjacent fins of a plurality of fins on the semiconductor substrate, forming a first liner above a perimeter including the recess, top surfaces of the semiconductor substrate, and top surfaces and sidewalls of the plurality of fins, the first liner includes a first oxide material, forming a second liner directly above the first liner, and forming a third liner directly above the second liner, the third liner includes a nitride material, the second liner includes a second oxide material capable of creating a dipole effect that neutralizes positive charges generated within the third liner and between the third liner and the first liner.