Invention Grant
- Patent Title: Semiconductor fabrication design rule loophole checking for design for manufacturability optimization
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Application No.: US15819213Application Date: 2017-11-21
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Publication No.: US10585346B2Publication Date: 2020-03-10
- Inventor: Chieh-Yu Lin , Dongbing Shao , Kehan Tian , Zheng Xu
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES, INC.
- Applicant Address: US NY Armonk KY
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION,GLOBALFOUNDRIES, INC.
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION,GLOBALFOUNDRIES, INC.
- Current Assignee Address: US NY Armonk KY
- Agency: Cantor Colburn LLP
- Agent Steven Meyers
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G03F1/36 ; G03F1/70 ; G03F1/38

Abstract:
Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.
Public/Granted literature
- US20190072846A1 SEMICONDUCTOR FABRICATION DESIGN RULE LOOPHOLE CHECKING FOR DESIGN FOR MANUFACTURABILITY OPTIMIZATION Public/Granted day:2019-03-07
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