Invention Grant
- Patent Title: Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework
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Application No.: US16224651Application Date: 2018-12-18
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Publication No.: US10585347B2Publication Date: 2020-03-10
- Inventor: Saravanapriyan Sriraman , Richard Wise , Harmeet Singh , Alex Paterson , Andrew D. Bailey, III , Vahid Vahedi , Richard A. Gottscho
- Applicant: Lam Research Corporation
- Applicant Address: US CA Fremont
- Assignee: Lam Research Corporation
- Current Assignee: Lam Research Corporation
- Current Assignee Address: US CA Fremont
- Agency: Weaver Austin Villeneuve & Sampson LLP
- Main IPC: G03F1/36
- IPC: G03F1/36 ; G06F17/50 ; G03F1/80 ; G03F1/70

Abstract:
Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
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