Invention Grant
- Patent Title: Silicon PMOS with gallium nitride NMOS for voltage regulation
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Application No.: US16078675Application Date: 2016-03-28
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Publication No.: US10600787B2Publication Date: 2020-03-24
- Inventor: Sansaptak Dasgupta , Han Wui Then , Marko Radosavljevic , Peter G. Tolchinsky , Roza Kotlyar , Valluri R. Rao
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- International Application: PCT/US2016/024420 WO 20160328
- International Announcement: WO2017/171699 WO 20171005
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/66 ; H01L29/06 ; H01L29/20 ; H01L29/778 ; H01L21/02 ; H01L21/28 ; H01L21/8258 ; H01L23/498 ; H01L23/544 ; H01L29/16 ; H01L29/205 ; H01L29/423 ; H01L29/04 ; H01L29/417 ; H01L21/8238 ; H04B1/38
Abstract:
This disclosure pertains to a gallium nitride transistor that is formed in a trench etched into a silicon substrate. A gallium nitride layer is on the trench of the silicon substrate. A source electrode and a drain electrode reside on the gallium nitride layer. A gate electrode resides on the gallium nitride layer between the source electrode and the drain electrode. A first polarization layer resides on the gallium nitride layer between the source electrode and the gate electrode, and a second polarization layer resides on the gallium nitride layer between the gate electrode and the drain electrode. The silicon substrate can include a silicon 111 substrate.
Public/Granted literature
- US20190051650A1 SILICON PMOS WITH GALLIUM NITRIDE NMOS FOR VOLTAGE REGULATION Public/Granted day:2019-02-14
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