Invention Grant
- Patent Title: Method, test line and system for detecting semiconductor wafer defects
-
Application No.: US15688889Application Date: 2017-08-29
-
Publication No.: US10605855B2Publication Date: 2020-03-31
- Inventor: Jing-Sen Wang , Yuan-Yao Chang , Hung-Chi Chiu , Chia-Wei Huang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: G01R31/26
- IPC: G01R31/26 ; H01L21/66 ; G01R31/28

Abstract:
A method, a test line and a system for detecting defects on a semiconductor wafer are presented. The method includes measuring a current-voltage (IV) curve of a plurality of metal oxide semiconductor (MOS) transistors which are connected in series in a test key; comparing the measured IV curve with a reference curve to obtain a first drain current drop in a linear region and a second drain current drop in a saturation region; and determining whether at least one of the MOS transistor among the MOS transistors of the test key is defected according to at least one of the first drain current drop and the second drain current drop.
Public/Granted literature
- US20190064250A1 METHOD, TEST LINE AND SYSTEM FOR DETECTING SEMICONDUCTOR WAFER DEFECTS Public/Granted day:2019-02-28
Information query