公开(公告)号：US10605855B2

公开(公告)日：2020-03-31

申请号：US15688889

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Sen Wang ,  Yuan-Yao Chang ,  Hung-Chi Chiu ,  Chia-Wei Huang

IPC: G01R31/26 ,  H01L21/66 ,  G01R31/28

Abstract: A method, a test line and a system for detecting defects on a semiconductor wafer are presented. The method includes measuring a current-voltage (IV) curve of a plurality of metal oxide semiconductor (MOS) transistors which are connected in series in a test key; comparing the measured IV curve with a reference curve to obtain a first drain current drop in a linear region and a second drain current drop in a saturation region; and determining whether at least one of the MOS transistor among the MOS transistors of the test key is defected according to at least one of the first drain current drop and the second drain current drop.

公开(公告)号：US20190064250A1

公开(公告)日：2019-02-28

申请号：US15688889

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Sen Wang ,  Yuan-Yao Chang ,  Hung-Chi Chiu ,  Chia-Wei Huang

IPC: G01R31/26 ,  G01R31/28

Abstract: A method, a test line and a system for detecting defects on a semiconductor wafer are presented. The method includes measuring a current-voltage (IV) curve of a plurality of metal oxide semiconductor (MOS) transistors which are connected in series in a test key; comparing the measured IV curve with a reference curve to obtain a first drain current drop in a linear region and a second drain current drop in a saturation region; and determining whether at least one of the MOS transistor among the MOS transistors of the test key is defected according to at least one of the first drain current drop and the second drain current drop.

公开(公告)号：US10510623B2

公开(公告)日：2019-12-17

申请号：US15855080

申请日：2017-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Wei Fang ,  Jing-Sen Wang ,  Yuan-Yao Chang ,  Wei-Ray Lin ,  Ting-Hua Hsieh ,  Pei-Hsuan Lee ,  Yu-Hsuan Huang

IPC: H01L21/66 ,  G03F7/20 ,  G06F17/50 ,  H01L21/768 ,  G01N21/88 ,  H01L21/76 ,  G01N21/95 ,  G01N21/93 ,  G06T7/00 ,  H01L21/8234

Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.