- 专利标题: Capacitive interconnect in a semiconductor package
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申请号: US15182091申请日: 2016-06-14
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公开(公告)号: US10609813B2公开(公告)日: 2020-03-31
- 发明人: Eng Huat Goh , Min Suet Lim , Fern Nee Tan , Khang Choong Yong , Jiun Hann Sir
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Eversheds Sutherland (US) LLP
- 主分类号: H05K1/14
- IPC分类号: H05K1/14 ; H01L23/498 ; H01G4/33 ; H01G4/228 ; H01G4/12 ; H05K1/02 ; H01L21/48 ; H01L23/50
摘要:
Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops.
公开/授权文献
- US20170359893A1 CAPACITIVE INTERCONNECT IN A SEMICONDUCTOR PACKAGE 公开/授权日:2017-12-14
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