Invention Grant
- Patent Title: Circuit, system and method for controlling read latency
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Application No.: US14636447Application Date: 2015-03-03
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Publication No.: US10658019B2Publication Date: 2020-05-19
- Inventor: Jongtae Kwak
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C7/22 ; G11C7/10 ; H03L7/081 ; H03K3/012 ; H03K3/037 ; H03L7/181

Abstract:
A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.
Public/Granted literature
- US20150170725A1 CIRCUIT, SYSTEM AND METHOD FOR CONTROLLING READ LATENCY Public/Granted day:2015-06-18
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