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166 条记录 (耗时 0.023 秒)

    Detecting irregularities in an input clock signal
    3.
    发明授权
    Detecting irregularities in an input clock signal 有权

    公开(公告)号：US11042180B1

    公开(公告)日：2021-06-22

    申请号：US16825027

    申请日：2020-03-20

    申请人： Arm Limited

    发明人： Ivan Michael Lowe ,  Mikael Yves Marie Rien

    IPC分类号： G06F1/06 ,  H03L7/181 ,  G06F1/08

    摘要： An apparatus has an input interface for receiving an input clock signal, and a plurality N of clock divider circuits, each clock divider circuit generating a corresponding monitored clock signal by dividing the input clock signal by N. Each clock divider circuit is arranged, when generating a leading edge of each clock cycle of its corresponding monitored clock signal, to use a leading edge of a different clock cycle of the input clock signal to the clock cycle of the input clock signal used by any other of the clock divider circuits. Analysis circuitry provided in association with each clock divider circuit produces a width indication for each clock cycle of the corresponding monitored clock signal. Alarm generation circuitry then triggers an alarm signal when, for any of the monitored clock signals, a variation in the width indication is detected over multiple clock cycles of that monitored clock signal.

    Phase locked loops
    7.
    发明授权
    Phase locked loops 有权

    公开(公告)号：US10193561B2

    公开(公告)日：2019-01-29

    申请号：US15384861

    申请日：2016-12-20

    申请人： Cirrus Logic International Semiconductor Ltd.

    发明人： John Paul Lesso

    IPC分类号： H03L7/06 ,  H03L7/091 ,  H03L7/099 ,  H03L7/181 ,  H03L7/085 ,  H03L7/089

    摘要： This application relates to methods and apparatus for phase locked loops. A phase-and-frequency detector (101) receives a reference clock signal (CKref) and a feedback signal (SFB) and outputs a first adjustment signal (U) that is modulated between respective first and second signal levels to provide control pulses indicating that an increase in frequency required for phase and frequency lock, and a second adjustment signal (D) that is modulated between respective first and second signal levels to provide control pulses indicating that a decrease in frequency required for phase and frequency lock. First and second time-to-digital converters (201-1 and 201-2) receive the first and second adjustment signals respectively and output respective first and second digital signals indicative of the duration of said control pulses. Each time-to-digital converter comprises a controlled-oscillator (401, 801) configured so as to operate at a first frequency when the respective adjustment signal is at the first signal level and operate at a second frequency when the respective adjustment signal is at the second signal level and a counter (403) configured to produce a count value of the number oscillations of the controlled-oscillator in each of a succession of count periods defined by a count clock signal. The first and second digital signals are based on the count values output from the respective counters. The difference between the first and second digital signals may be determined and input to digital loop filter (203) before driving numerically-controlled-oscillator (204) to produce the output signal.

    High accuracy clock synchronization circuit
    8.
    发明授权
    High accuracy clock synchronization circuit 有权

    公开(公告)号：US10171094B2

    公开(公告)日：2019-01-01

    申请号：US15492573

    申请日：2017-04-20

    申请人： SEIKO EPSON CORPORATION

    发明人： Katsuhito Nakajima

    IPC分类号： H03L7/095 ,  H03L7/099 ,  H03L7/181

    摘要： A circuit device includes a phase comparator that performs phase comparison between an input signal based on an oscillation signal and a reference signal, a processor that performs a signal process on frequency control data based on a result of the phase comparison, and an oscillation signal generation circuit that generates the oscillation signal having an oscillation frequency which is set on the basis of frequency control data having undergone the signal process. The phase comparator includes a counter that performs a count operation by using the input signal, and performs the phase comparison by comparing a count value in the counter inn (where n is an integer of 2 or more) cycles of the reference signal with an expected value of the count value in integers.